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參數(shù)資料
| 型號： | UPD46128512-E11X |
| 廠商： | NEC Corp. |
| 英文描述： | 128M-BIT CMOS MOBILE SPECIFIED RAM 8M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION |
| 中文描述： | 128兆位CMOS移動指明內(nèi)存800萬字由16位溫度范圍 |
| 文件頁數(shù)： | 17/82頁 |
| 文件大小： | 817K |
| 代理商： | UPD46128512-E11X |
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Preliminary Data Sheet M17507EJ2V0DS
17
μ
PD46128512-X
4.4 Single Write
Single write operation is a single-word length synchronous write operation. The
μ
PD46128512-X is supporting two
type of synchronous write operation, “Burst Read & Single Write” and “Burst Read & Burst Write”, configurable with SW
bit in the mode register. When the device set to the “Burst Read & Single Write” operation mode, the burst length at the
synchronous write operation is always fixed to single word length regardless of the burst length (BL) setting in the mode
register, however, BL setting is still effective in synchronous read operation (Refer to
5. Mode Register Settings
).
Refer to
Figure 8-8. Synchronous Burst Write Cycle Timing Chart (/WE level Control)
,
Figure 8-9.
Synchronous Burst Write Cycle Timing Chart (/WE single clock control)
,
Figure 8-10. Synchronous Single Write
Timing Chart.
4.5 /WE Control
The
μ
PD46128512-X is supporting two type of timing control with /WE input signal, “/WE level control” and “/WE single
clock control” configurable with WC bit in the mode register at synchronous write operation. In case of /WE level
controlling, /WE must be asserted LOW before the 2nd clock input timing (T1).
Refer to
Figure 8-8. Synchronous Burst Write Cycle Timing Chart (/WE level Control)
,
Figure 8-9.
Synchronous Burst Write Cycle Timing Chart (/WE single clock control)
.
Figure 4-2. /WE Control
T1
T0
T3
T2
T4
T5
T6
T7
CLK (Input)
/ADV (Input)
Address (Input)
/CE1 (Input)
/WE (Input)
DQ0 to DQ15 (Input)
/WAIT (Output)
/WE (Input)
DQ0 to DQ15 (Input)
/WAIT (Output)
/WE Level Control
/WE Single Clock Control
Add
Read Latency = 5
t
WES
High-Z
D0
D1
D2
D3
High-Z
t
WES
t
WEH
High-Z
D0
D1
D2
D3
High-Z
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