參數(shù)資料
型號(hào)： UPD46128512F9-CR2
廠商： NEC Corp.
英文描述： 128M-BIT CMOS MOBILE SPECIFIED RAM 8M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
中文描述： 128兆位CMOS移動(dòng)指明內(nèi)存800萬字由16位溫度范圍
文件頁(yè)數(shù)： 32/82頁(yè)
文件大?。?/td> 817K
代理商： UPD46128512F9-CR2
Preliminary Data Sheet M17507EJ2V0DS
32
μ
PD46128512-X
5.12 Cautions for Timing Chart of Setting Mode Register
Timing charts for setting mode register are following 3 methods.
<Setting 1> Setting method by CLK fixed HIGH or LOW at asynchronous timing (asynchronous timing)
<Setting 2> Setting method by toggling CLK at asynchronous timing (asynchronous timing+ toggle CLK)
<Setting 3> Setting method at synchronous timing (synchronous timing)
For timing chart, refer to
Figure 9-1. Mode Register Setting Timing Chart (asynchronous timing+ CLK fixed
LOW/HIGH), Figure 9-2. Mode Register Setting Timing Chart (asynchronous timing+ toggle CLK), Figure 9-3.
Mode Register Setting Timing Chart (synchronous timing)
.
It is recommended to set Mode Register contents through <Setting 1>, since <Setting 1> is used regardless of device
status, asynchronous or synchronous.
<Setting 2> procedure can be performed when the device is in the asynchronous (page) mode. In case the mode
register setting is possible only with <Setting 2> procedure, “reset to page” function using the CE2 signal toggling will be
required in changing the operation from synchronous (burst) mode to asynchronous (page) mode. (Refer to
4.11 Reset
Function from Synchronous Burst Mode to Asynchronous Page Mode
)
<Setting 3> procedure can be performed when the device is in the synchronous (burst) mode.
Figure 5-1. Mode Register Setting State Machine
Power On
Asynchronous Mode
(Default)
Synchronous
Mode
Asynchronous
Mode
<Setting 1>
<Setting 2>
<Setting 1>
<Setting 2>
<Setting 1>
<Setting 2>
<Setting 1>
<Setting 2>
<Setting 1>
<Setting 3>
<Setting 1>
<Setting 3>
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