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參數(shù)資料
| 型號： | UPD4990AC |
| 廠商： | NEC Corp. |
| 英文描述： | SERIAL I/O CALENDAR & CLOCK CMOS LSI |
| 中文描述： | 串行I / O日歷 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 129K |
| 代理商： | UPD4990AC |
μ
PD4990A
10
°
Test mode
In the test mode, data is output to the DATA OUT pin regardless of whether data has been input to OUT
ENBL.
There are two different test modes depending on the OUT ENBL data.
(1) Test mode 1 (OUT ENBL = 0)
8 192 Hz signals are set parallel in the counters for year, month, week, day, time, minute, and second.
There is no carry from these counters.
(2) Test mode 2 (OUT ENBL = 1)
A 8 192 Hz signal is input to the second counter instead of the 1 Hz signal. There is carry from counters.
Outputs from DATA OUT and TP OUT pins in different function modes are listed below.
MODE
DATA OUT
TP
Others
REGISTER HOLD
1 Hz
64 Hz
By this command, TEST MODE is released.
REGISTER SHIFT
LSB of shift register
32 Hz
8 192 Hz input to time counter
TIME SET
LSB of shift register
L Level
Test mode
TIME READ
1 Hz
32 Hz
8 192 Hz input to time counter
When the REGISTER HOLD command cancels the test mode, 64 Hz is output to the TP pin.
Year
counter
8 192 Hz
Month
counter
Week
counter
Day
counter
Time
counter
Minute
counter
Second
counter
Year
counter
8 192 Hz
Month
counter
Week
counter
Day
counter
Time
counter
Minute
counter
Second
counter
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