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參數(shù)資料
| 型號： | UPD4990AC |
| 廠商： | NEC Corp. |
| 英文描述： | SERIAL I/O CALENDAR & CLOCK CMOS LSI |
| 中文描述： | 串行I / O日歷 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 129K |
| 代理商： | UPD4990AC |
μ
PD4990A
12
TIMING DIAGRAM FOR SETTING COMMANDS (C
0
, C
1
, C
2
)
Figure 3.
V
DD
V
SS
= 2.0 V
t
SU
t
HLD
= 1
μ
s MIN.
t
STB
= 1
μ
s MIN.
t
d1
= 1
μ
s MAX. (Other than time read mode)
t
d2
= 20
μ
s MAX. (Time read mode)
t
S-C
= 1
μ
s MIN.
= 1
μ
s MIN.
Note:
A mode is latched by STB and held until another mode in the same group is set.
Other than time read mode
Time read mode
OLD MODE
NEW COMMAND
VALID
OLD MODE
NEW MODE
NEW MODE
V
IH
V
IL
CAN CHANGE
CAN CHANGE
STABLE
V
IH
V
IL
V
IH
V
IL
V
IH
C
2
,C
1
,C
0
CS
STB
CLK
V
IH
V
IL
t
SU
t
HLD
t
SU
t
HLD
t
STB
t
S-C
t
S-C
t
d2
t
d1
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