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參數(shù)資料
| 型號： | UPD4990AC |
| 廠商： | NEC Corp. |
| 英文描述： | SERIAL I/O CALENDAR & CLOCK CMOS LSI |
| 中文描述： | 串行I / O日歷 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 129K |
| 代理商： | UPD4990AC |
μ
PD4990A
16
14PIN PLASTIC DIP (300 mil)
P14C-100-300A,C-1
ITEM
A
B
C
MILLIMETERS
20.32 MAX.
INCHES
0.800 MAX.
0.100 MAX.
0.100 (T.P.)
NOTES
1) Each lead centerline is located within 0.25 mm (0.01 inch) of
its true position (T.P.) at maximum material condition.
D
0.50±0.10
0.020–0.005
2.54 MAX.
2.54 (T.P.)
N
R
0~15
°
0.25
0.01
0~15
°
2) Item "K" to center of leads when formed parallel.
M
0.25
0.010–0.003
F
G
H
I
J
K
L
1.2 MIN.
3.5±0.3
0.047 MIN.
0.138±0.012
0.020 MIN.
0.170 MAX.
0.200 MAX.
0.300 (T.P.)
0.252
0.51 MIN.
4.31 MAX.
5.08 MAX.
7.62 (T.P.)
6.4
+0.10
–0.05
M
R
M
I
G
H
F
B
N
C
D
14
8
1
7
A
J
K
L
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