參數(shù)資料
型號: UPD4991A
廠商: NEC Corp.
英文描述: 4-BIT PARALLEL I/O CALENDAR CLOCK
中文描述: 4位并行I / O日歷鐘
文件頁數(shù): 23/32頁
文件大?。?/td> 133K
代理商: UPD4991A
μ
PD4991A
23
BUSY output
The BUSY signal can be output to the TP
1
and TP
2
pins.
When output of the BUSY signal is specified, only the BUSY signal is output to the TP
1
and TP
2
pins.
The contents of the CONTROL REGISTER 2 are not affected, however.
Fig. 8 BUSY Output Waveform
Fig. 9 shows an example of an application using TP
2
.
Fig. 9 TP
2
Output Status
1 pulse
REPEAT
Output status
ENABLE
TP
2
30.5 s
RESET & RUN
T
T
t
1
t
2
T
T
30.5 s
μ
Interval
CLK STOP
RUN
RESET & RUN
Interval
CLK STOP
RUN
RESET
RESET
30.5 s
t
1
+ t
2
= T
T
TP
2
flag ON
Note
When the output status is disabled, the signal goes “H” regardless of the status of TP
2
.
BUSY
BUSY signal
1st digit carry
1st digit carry
457.7 s
BUSY flag
OFF
BUSY flag
ON
BUSY flag
ON
TP
1
or TP
2
Output DISABLE SET
30.5 s
μ
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