參數(shù)資料
型號(hào)： UPD4991A
廠(chǎng)商： NEC Corp.
英文描述： 4-BIT PARALLEL I/O CALENDAR CLOCK
中文描述： 4位并行I / O日歷鐘
文件頁(yè)數(shù)： 4/32頁(yè)
文件大?。?/td> 133K
代理商： UPD4991A
μ
PD4991A
4
PIN FUNCTION
WE..................... Write control pin (input).
The contents of the data bus are written to an address specified by the address bus at the
rising edge of WE.
OE ..................... Read control pin (input).
While OE = “L” level, the contents specified by the address bus are read to the data bus.
A
3
to A
0
.............. Address bus pins (input).
These pins specify an internal address of the
μ
PD4991A.
D
3
to D
0
............. Data bus pin (I/O).
These pins constitute a bidirectional bus.
CS
1
, CS
2
........... Chip select pins (input).
When CS
1
= “L” and CS
2
= “H”, data can be transferred between the
μ
PD4991A and the CPU.
TP
1
.................... Timing pulse pin (output) (N-ch open-drain).
Outputs an alarm coincidence signal.
TP
2
.................... Timing pulse pin (output) (N-ch open-drain).
Outputs an interval timer signal.
X
IN
...................... Crystal oscillation signal pin (input).
Inverter input for oscillation.
X
OUT
................... Crystal oscillation signal pin (output).
Inverter output for oscillation.
V
DD
..................... Positive power supply pin.
V
SS
..................... GND pin.
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