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參數(shù)資料
| 型號： | UPD4991A |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT PARALLEL I/O CALENDAR CLOCK |
| 中文描述： | 4位并行I / O日歷鐘 |
| 文件頁數(shù)： | 26/32頁 |
| 文件大?。?/td> | 133K |
| 代理商： | UPD4991A |
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μ
PD4991A
26
AC Timing of
μ
PD4991
2.
Function
PARAMETER
μ
PD4991
μ
PD4991A
Valid Range of
±
30 s ADJUST
1-second to 1-minute digits
(no carry to 10-minute digit)
All digits
BUSY Flag when
±
30 s ADJUST
Not BUSY
BUSY until all digits are carried
D
3
bit of CONTROL REGISTER 1
NOP
CLOCK WAIT
CLOCK WAIT Bit and CLOCK STOP Bit
Both bits inhibit input of clock to the clock counter (1 Hz) and subsequently stop the clock. The CLOCK STOP
bit is used to set the time to the clock (be sure to stop the clock when setting it). The CLOCK WAIT bit is used
to prevent the CPU from reading wrong data in case counting takes place when the time is read (the time can
also be read without the CLOCK WAIT bit but with the BUSY signal or by performing two reads). If the clock
is run within 0.5 second after stopping the clock or placed in the wait state, no delay in respect to the actual
time occurs.
AC Timing of
μ
PD4991A
WE or CS
D
0
~ D
3
t
DW
t
DH
50%
50%
WE or CS
D
0
~ D
3
t
DW
t
DH
50%
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|---|---|
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參數(shù)描述 |
|---|---|
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