參數(shù)資料
型號: UPD70208HLP-16
廠商: NEC Corp.
英文描述: V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR
中文描述: V40HLTM,V50HLTM 16 / 8,16位微處理器
文件頁數(shù): 44/110頁
文件大小: 625K
代理商: UPD70208HLP-16
4
μ
P
D
AC CY V
P
S
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Instruc-
tion
Group
Mnemonic
Operand(s)
Operation
Operation Code
Flags
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
reg, reg’
mem, reg
reg, mem
reg, imm
mem, imm
acc, imm
reg, reg’
mem, reg
reg, mem
reg, imm
mem, imm
acc, imm
reg, reg’
mem, reg
reg, mem
reg, imm
mem, imm
acc, imm
reg, reg’
mem, reg
reg, mem
reg, imm
mem, imm
acc, imm
0 0 0 0 0 0 1 W
0 0 0 0 0 0 0 W
0 0 0 0 0 0 1 W
1 0 0 0 0 0 s W
1 0 0 0 0 0 s W
0 0 0 0 0 1 0 W
0 0 0 1 0 0 1 W
0 0 0 1 0 0 0 W
0 0 0 1 0 0 1 W
1 0 0 0 0 0 s W
1 0 0 0 0 0 s W
0 0 0 1 0 1 0 W
0 0 1 0 1 0 1 W
0 0 1 0 1 0 0 W
0 0 1 0 1 0 1 W
1 0 0 0 0 0 s W
1 0 0 0 0 0 s W
0 0 1 0 1 1 0 W
0 0 0 1 1 0 1 W
0 0 0 1 1 0 0 W
0 0 0 1 1 0 1 W
1 0 0 0 0 0 s W
1 0 0 0 0 0 s W
0 0 0 1 1 1 0 W
1 1 reg reg’
mod reg mem
mod reg mem
1 1 0 0 0 reg
mod
0 0 0 mem
1 1 reg reg’
mod reg mem
mod reg mem
1 1 0 1 0 reg
mod
0 1 0
mem
1 1 reg reg’
mod reg mem
mod reg mem
1 1 1 0 1 reg
mod
1 0 1
mem
1 1 reg reg’
mod reg mem
mod reg mem
1 1 0 1 1 reg
mod
0 1 1 mem
2
2-4
2-4
3-4
3-6
2-3
2
2-4
2-4
3-4
3-6
2-3
2
2-4
2-4
3-4
3-6
2-3
2
2-4
2-4
3-4
3-6
2-3
reg
reg + reg’
(mem)
(mem) + reg
reg
reg + (mem)
reg
reg + imm
(mem)
(mem) + imm
If W = 0: AL
AL + imm
If W = 1: AW
AW + imm
reg
reg + reg’+ CY
(mem)
(mem) + reg + CY
reg
reg + (mem) + CY
reg
reg + imm + CY
(mem)
(mem) + imm + CY
If W = 0: AL
AL + imm + CY
If W = 1: AW
AW + imm + CY
reg
reg – reg’
(mem)
(mem) – reg
reg
reg – (mem)
reg
reg – imm
(mem)
(mem) – imm
If W = 0: AL
AL – imm
If W = 1: AW
AW – imm
reg
reg – reg’– CY
(mem)
(mem) – reg – CY
reg
reg – (mem) – CY
reg
reg – imm – CY
(mem)
(mem) – imm – CY
If W = 0: AL
AL – imm – CY
If W = 1: AW
AW imm– CY
2
13/21
10/14
4
15/23
4
2
13/21
10/14
4
15/23
4
2
13/21
10/14
4
15/23
4
2
13/21
10/14
4
15/23
4
ADD
ADDC
SUB
SUBC
A
Bytes
Clock Cycles
V40HL V50HL
2
13/21
10/14
4
15/23
4
2
13/21
10/14
4
15/23
4
2
13/21
10/14
4
15/23
4
2
13/21
10/14
4
15/23
4