參數(shù)資料
型號(hào): UPD70208HLP-16
廠商: NEC Corp.
英文描述: V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR
中文描述: V40HLTM,V50HLTM 16 / 8,16位微處理器
文件頁(yè)數(shù): 47/110頁(yè)
文件大?。?/td> 625K
代理商: UPD70208HLP-16
4
μ
P
D
AC CY V
P
S
Z
Instruc-
tion
Group
Mnemonic
Operand(s)
Bytes
Operation
Operation Code
Flags
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
reg8
mem8
reg16
mem16
1 1 1 1 0 1 1 0
1 1 1 1 0 1 1 0
1 1 1 1 0 1 1 1
1 1 1 1 0 1 1 1
1 1 1 1 0 reg
mod
1 1 0 mem
1 1 1 1 0 reg
mod
1 1 0 mem
2
2-4
2
2-4
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
temp
AW
If temp
÷
reg8
FFH
AH
temp%reg8, AL
temp
÷
reg8
If temp
÷
reg8 > FFH
TA
(001H, 000H), TC
(003H, 002H)
SP
SP – 2, (SP + 1, SP)
PSW, IE
0, BRK
0
SP
SP – 2, (SP + 1, SP)
PS, PS
TC
SP
SP – 2, (SP + 1, SP)
PC, PC
TA
temp
AW
If temp
÷
(mem8)
FFH
AH
temp%(mem8), AL
temp
÷
(mem8)
If temp
÷
(mem8) > FFH
TA
(001H, 000H), TC
(003H, 002H)
SP
SP – 2, (SP + 1, SP)
PSW, IE
0, BRK
0
SP
SP – 2, (SP + 1, SP)
PS, PS
TC
SP
SP – 2, (SP + 1, SP)
PC, PC
TA
temp
DW, AW
If temp
÷
reg16
FFFFH
DW
temp%reg16, AW
temp
÷
reg16
If temp
÷
reg16 > FFFFH
TA
(001H, 000H), TC
(003H, 002H)
SP
SP – 2, (SP + 1, SP)
PSW, IE
0, BRK
0
SP
SP – 2, (SP + 1, SP)
PS, PS
TC
SP
SP – 2, (SP + 1, SP)
PC, PC
TA
temp
DW, AW
If temp
÷
(mem16)
FFFFH
DW
temp%(mem16), AW
temp
÷
(mem16)
If temp
÷
(mem16) > FFFFH
TA
(001H, 000H), TC
(003H, 002H)
SP
SP – 2, (SP + 1, SP)
PSW, IE
0, BRK
0
SP
SP – 2, (SP + 1, SP)
PS, PS
TC
SP
SP – 2, (SP + 1, SP)
PC, PC
TA
19
24
25
34
DIVU
U
Clock Cycles
V40HL V50HL
19
24
25
30/34
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