參數(shù)資料
型號: UPD70208HLP-16
廠商: NEC Corp.
英文描述: V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR
中文描述: V40HLTM,V50HLTM 16 / 8,16位微處理器
文件頁數(shù): 65/110頁
文件大?。?/td> 625K
代理商: UPD70208HLP-16
6
μ
P
D
AC CY V
P
S
Z
Instruc-
tion
Group
Mnemonic
Operand(s)
Bytes
Operation
Operation Code
Flags
7 6 5 4 3 2 1 0
1 1 1 1 0 1 0 0
1 0 0 1 1 0 1 1
1 1 1 1 1 0 1 0
1 1 1 1 1 0 1 1
1 1 1 1 0 0 0 0
1 1 0 1 1
X X X
1 1 0 1 1
X X X
0 1 1 0 0 1 1
X
0 1 1 0 0 1 1
X
1 0 0 1 0 0 0 0
0 0 1
sreg
1 1 0
1
1
1
1
1
2
2-4
2
2-4
1
1
7 6 5 4 3 2 1 0
CPU Halt
Poll and wait
n: Number of times POLL pin is sampled
IE
0
IE
1
Bus Lock Prefix
No Operation
data bus
(mem)
No Operation
data bus
(mem)
No Operation
Segment override prefix
2
2 + 5n
2
2
2
2
14
2
14
3
2
HALT
POLL
DI
EI
BUSLOCK
FPO1
FPO2
NOP
*
fp-op
fp-op, mem
fp-op
fp-op, mem
1 1
Y Y Y Z Z Z
mod
Y Y Y
mem
1 1
Y Y Y Z Z Z
mod
Y Y Y
mem
Clock Cycles
V40HL V50HL
C
AC CY V
P
S
Z
Instruc-
tion
Group
Mnemonic
Operand(s)
Bytes
Operation
Operation Code
Flags
7 6 5 4 3 2 1 0
1 1 1 0 1 1 0 1
1 1 1 0 1 1 0 1
2
3
7 6 5 4 3 2 1 0
PC
(SP + 1, SP), PS
(SP + 3, SP + 2),
PSW
(SP + 5, SP + 4), SP
SP + 6, MD is set to write
disabled
TA
(4n + 1, 4n), TC
(4n + 3, 4n + 2)
SP
SP – 2, (SP + 1, SP)
PSW, MD
1
SP
SP – 2, (SP + 1, SP)
PS, PS
TC
SP
SP – 2, (SP + 1, SP)
PC, PC
TA
n = imm8
39
58
RETEM
CALLN
imm8
1 1 1 1 1 1 0 1
1 1 1 0 1 1 0 1
8
R
R
R
R
R
R
*
DS0:, DS1:, PS:, and SS:.
2
2 + 5n
2
2
2
2
10/14
2
10/14
3
2
Clock Cycles
V40HL V50HL
27/39
38/58
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