參數(shù)資料
型號: UPD703100-40
廠商: NEC Corp.
英文描述: V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: V850E/MS1TM 32/16單晶片微控制器
文件頁數(shù): 27/132頁
文件大?。?/td> 1174K
代理商: UPD703100-40
Preliminary Data Sheet U14168EJ2V0DS00
27
μ
PD703100A-33, 703100A-40, 703101A-33, 703102A-33
6.3 DRAM Controller
6.3.1 Features
{
Generates the RAS, UCAS, and LCAS signals
{
Can be connected directly to high-speed page DRAM and EDO DRAM
{
Supports RAS hold mode
{
Can assign 4 types of DRAM to 8 memory block space
{
Supports 2CAS type DRAM
{
Can be switched between row and column address multiplex widths
{
Can insert waits (0 to 3 waits) at each of the following timings
Row address pre-charge wait
Row address hold wait
Data access wait
Column address pre-charge wait
{
Supports CBR refresh and CBR self refresh
6.3.2 DRAM connections
The following figure shows DRAM connection examples.
Figure 6-3. DRAM Connection Examples (1/2)
(a) 16-Mbit (1 M
×
16) DRAM
16-Mbit (1 M
×
16) DRAM
RAS
LCAS
UCAS
WE
OE
A0 to A9
I/O1 to I/O16
A1 to A10
D0 to D15
RASn
LCAS
V850E/MS1
UCAS
WE
OE
Remark
n = 0 to 7
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