
CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION
User
’
s Manual U15862EJ3V0UD
529
Reset by setting the CSIAEn bit of the CSIMAn register to 0
Transfer of 1 byte is complete by setting the ATSTPn bit of the CSITn register to 1
Transfer of the range specified by the ADTPn register is complete
At this time, an interrupt request signal (INTCSIAn) is generated except when the CSIAEn bit = 0.
If a transfer is terminated in the middle, transfer starting from the remaining data is not possible. Read
automatic data transfer address count register n (ADTCn) to confirm how much of the data has already
been transferred, set the transfer data again, and then re-execute transfer.
Figure 17-5 shows the operation timing in automatic transmission/reception mode and Figure 17-6 shows
the operation flowchart. Figure 17-7 shows the operation of internal buffer RAM when 6 bytes of data are
transmitted/received.
Figure 17-5. Automatic Transmission/Reception Mode Operation Timings
SCKAn
SOAn
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
CSIAFn
TSFn
SIAn
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Interval
Cautions 1. Because, in the automatic transmission/reception mode, the automatic
transmit/receive function writes/reads data to/from the internal buffer RAM after
1-byte transmission/reception, an interval is inserted until the next
transmission/reception. As the buffer RAM write/read is performed at the same
time as CPU processing, the interval is dependent upon the value of automatic
data transfer interval specification register n (ADTIn) (see (4) Automatic
transmit/receive interval time).
2. When the TSFn bit is cleared, the SOAn pin becomes low level.
Remarks 1.
CSIAFn: Interrupt request flag
TSFn:
2.
n = 0 (V850ES/KF1)
n = 0, 1 (V850ES/KG1, V850ES/KJ1)
Bit n of serial status register n (CSISn)