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型號(hào)：	UPD703212
廠商：	NEC Corp.
英文描述：	32-Bit Single-Chip Microcontrollers
中文描述：	32位單芯片微控制器
文件頁(yè)數(shù)：	622/757頁(yè)
文件大?。?/td>	4410K
代理商：	UPD703212

CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION

s Manual U15862EJ3V0UD

19.3 Maskable Interrupts

Maskable interrupt requests can be masked by interrupt control registers. The V850ES/KF1, V850ES/KG1, and

V850ES/KJ1 have 33 to 45 maskable interrupt sources (refer to

19.1.1 Features

If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to

the default priority. In addition to the default priority, eight levels of interrupt priorities can be specified by using the

interrupt control registers, allowing programmable priority control.

When an interrupt request has been acknowledged, the interrupt disabled (DI) status is set and the

acknowledgement of other maskable interrupts is disabled.

When the EI instruction is executed in an interrupt servicing routine, the interrupt enabled (EI) status is set, which

enables acknowledgement of interrupts having a priority higher than that of the interrupt request currently in progress.

Note that only interrupts with a higher priority have this capability; interrupts with the same priority level cannot be

To use multiple interrupts, it is necessary to save EIPC and EIPSW to memory or a register before executing the EI

instruction, and restore EIPC and EIPSW to the original values by executing the DI instruction before the RETI

instruction.

When the WDTM14 bit of watchdog timer mode register 1 (WDTM1) is set to 0, the watchdog timer overflow

interrupt functions as a maskable interrupt (INTWDTM1).

19.3.1 Operation

If a maskable interrupt request is generated, the CPU performs the following processing and transfers control to a

handler routine.

<1> Saves the restored PC to EIPC.

<2> Saves the current PSW to EIPSW.

<3> Writes an exception code to the lower halfword of ECR (EICC).

<4> Sets the ID bit of the PSW and clears the EP bit.

<5> Loads the corresponding handler address to the PC and transfers control.

The maskable interrupt request masked by INTC and the maskable interrupt request that occurs while another

interrupt is being serviced (when PSW.NP = 1 or PSW.ID = 1) are held pending internally. When the interrupts are

unmasked, or when PSW.NP = 0 and PSW.ID = 0 by using the RETI and LDSR instructions, a new maskable

interrupt servicing is started in accordance with the priority of the pending maskable interrupt request.

Figure 19-4 shows the servicing flow for maskable interrupts.

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
UPD703212A	制造商:NEC 制造商全稱:NEC 功能描述:32-Bit Single-Chip Microcontrollers
UPD703212A1	制造商:NEC 制造商全稱:NEC 功能描述:32-Bit Single-Chip Microcontrollers
UPD703212A2	制造商:NEC 制造商全稱:NEC 功能描述:32-Bit Single-Chip Microcontrollers
UPD703212GCA1-XXX-8EU	制造商:NEC 制造商全稱:NEC 功能描述:32-Bit Single-Chip Microcontrollers
UPD703212GCA2-XXX-8EU	制造商:NEC 制造商全稱:NEC 功能描述:32-Bit Single-Chip Microcontrollers

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