參數(shù)資料
型號: UPD720122
廠商: NEC Corp.
英文描述: MOS Integrated Circuit
中文描述: 馬鞍山集成電路
文件頁數(shù): 70/82頁
文件大?。?/td> 650K
代理商: UPD720122
Data Sheet S16685EJ2V0DS
70
μ
PD720122
Figure 2-11. USB Receiver Jitter Tolerance for Full-Speed
Differential
data lines
Paired
transitions
N * T
PERIOD
+ T
xJR2
T
PERIOD
Consecutive
transitions
N * T
PERIOD
+ T
xJR1
T
xJR
T
xJR1
T
xJR2
(3) USB connection sequence on USB1.1 bus
The PHY core implemented on the
μ
PD720122 automatically determines the Up port.
Check the SP_MODE bit (SP_MODE) of the Int Status 2 register after an EPC2_STG bus reset interrupt has
occurred to determine whether the USB is connected to FS or HS.
Figure 2-12. USB Connection Sequence on USB 1.1 Bus
t
HDS
t
SCA
t
CKO
t
CKI
t
SCS
t
FCA
t
DRS
Chirp K device out
Reversion to full-speed mode
FS J
FS J
Pull-up is active.
T
0
High
USB bus
USBRST
SPMODE
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