參數(shù)資料
型號(hào)： UPD7281
廠商： NEC Corp.
英文描述： IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER
中文描述： IEEE1394連接的OHCI 1.1標(biāo)準(zhǔn)3PORT物理層鏈路1 -芯片的主機(jī)控制器
文件頁(yè)數(shù)： 15/40頁(yè)
文件大小： 297K
代理商： UPD7281
Preliminary Data Sheet S15306EJ2V0DS
15
μ
PD72874
Table
2-1. Bit Field Description (3/3)
Field
Size
R/W
Reset value
Description
Timeout
1
R/W
0
Arbitration state machine time-out.
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
Port_event
1
R/W
0
Set to 1 when the Int_enable bit in the register map of each port is 1 and
there is a change in the ports connected, Bias, Disabled and Fault bits.
Set to 1 when the Watchdog bit is 1 and any one port does resume.
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
Enab_accel
1
R/W
0
Enables arbitration acceleration.
Ack-acceleration and Fly-by arbitration are enabled.
1: Enabled
0: Disabled
If this bit changes while the bus request is pending, the operation is not
guaranteed.
Enab_multi
1
R/W
0
Enable multi-speed packet concatenation.
Setting this bit to 1 follows multi-speed transmission.
When this bit is set to 0,the packet will be transmitted with the same speed
as the first packet.
Page_select
3
R/W
000
Select page address between 1000 to 1111.
000: Port Status Page
001: Vendor ID Page
111: Vendor Dependent Page
Others: Unused
Port_select
4
R/W
0000
Port Selection.
Selecting 000 (Port Status Page) with the Page_select selects the port.
Selecting 111 (Vendor Dependent Page) with the Page_select have to select
the Port 1.
0000: Port 0
0001: Port 1
0010: Port 2
Others: Unused
Reserved
-
R
000…
Reserved. Read as 0.
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