參數(shù)資料
型號(hào): UPD7281
廠商: NEC Corp.
英文描述: IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER
中文描述: IEEE1394連接的OHCI 1.1標(biāo)準(zhǔn)3PORT物理層鏈路1 -芯片的主機(jī)控制器
文件頁數(shù): 5/40頁
文件大?。?/td> 297K
代理商: UPD7281
Preliminary Data Sheet S15306EJ2V0DS
5
μ
PD72874
PIN NAME
AD0 to AD31
: PCI Multiplexed Address and Data
CARD_ON
: PCI/Card Select
CBE0 to
CBE3
CLKRUN
: PCICLK Running
CPS
: Cable Power Status Input
D3CSUP
: D3cold Support
DEVSEL
: Device Select
FRAME
: Cycle Frame
GND
: GND
GNT
: Bus_master Grant
GROM_EN : Serial EEPROM Enable
GROM_SCL
: Serial EEPROM Clock Output
GROM_SDA
: Serial EEPROM Data Input / Output
IC(H)
: Internally Connected (High Clamped)
IC(L)
: Internally Connected (Low Clamped)
IC(N)
: Internally Connected (Open)
IDSEL
: ID Select
INTA
: Interrupt
IRDY
: Initiator Ready
L_V
DD
: V
DD
for Link Digital Core and Link I/Os
PAR
: Parity
PC0 to PC2
: Power Class Input
PCI_V
DD
: V
DD
for PCI I/Os
PCLK
: PCI Clock
PERR
: Parity Error
PME
: PME Output
PRST
: Reset
: Command/Byte Enables
P_AV
DD
P_DV
DD
P_RESET
REQ
RI0
RI1
RSMRST
SERR
STOP
TpA0n
TpA0p
TpA1n
TpA1p
TpA2n
TpA2p
TpB0n
TpB0p
TpB1n
TpB1p
TpB2n
TpB2p
TpBias0
TpBias1
TpBias2
TRDY
XI
XO
: PHY Analog V
DD
: PHY Digital V
DD
: PHY Power on Reset Input
: Bus_master Request
: Resistor0 for Reference Current Setting
: Resistor1 for Reference Current Setting
: Resume Reset
: System Error
: PCI Stop
: Port-1 Twisted Pair A Negative Input/Output
: Port-1 Twisted Pair A Positive Input/Output
: Port-2 Twisted Pair A Negative Input/Output
: Port-2 Twisted Pair A Positive Input/Output
: Port-3 Twisted Pair A Negative Input/Output
: Port-3 Twisted Pair A Positive Input/Output
: Port-1 Twisted Pair B Negative Input/Output
: Port-1 Twisted Pair B Positive Input/Output
: Port-2 Twisted Pair B Negative Input/Output
: Port-2 Twisted Pair B Positive Input/Output
: Port-3 Twisted Pair B Negative Input/Output
: Port-3 Twisted Pair B Positive Input/Output
: Port-1 Twisted Pair Bias Voltage Output
: Port-2 Twisted Pair Bias Voltage Output
: Port-3 Twisted Pair Bias Voltage Output
: Target Ready
: X’tal XI
: X’tal XO
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