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Preliminary Data Sheet S15305EJ2V0DS
22
μ
PD72873
3.1.11 Offset_10 Base Address 0 Register
This register specifies the base memory address for accessing all the “Operation registers” (i.e. control,
configuration, and status registers) of the
μ
PD72873, while the BIOS is expected to set this value during power-up
reset.
Bits
R/W
Description
11-0
R
Constant value of 000H. These bits are “read-only”.
31-12
R/W
-
3.1.12 Offset_2C Subsystem Vendor ID Register
This register identifies the subsystem that contains the NEC’s
μ
PD72873 function. While the ID is assigned by the
PCI_SIG committee, the value should be loaded into the register from the external serial ROM after power-up reset.
Access to this register through PCI-bus is prohibited.
Bits
R/W
Description
15-0
R
Default value of 1033H.
3.1.13 Offset_2E Subsystem ID Register
This register identifies the type of the subsystem that contains the NEC’s
μ
PD72873 function. While the ID is
assigned by the manufacturer, the value should be loaded into the register from the external serial EEPROM after
power-up reset. Access to this register through PCI-bus is prohibited.
Bits
R/W
Description
15-0
R
Default value of 00E7H.
3.1.14 Offset_34 Cap_Ptr Register
This register points to a linked list of additional capabilities specific to the
μ
PD72873, the NEC’s implementation of
the 1394 OHCI specification.
Bits
R/W
Description
7-0
R
Constant value of 60H. The value represents an offset into the
μ
PD72873’s PCI Configuration
Space for the location of the first item in the New Capabilities Linked List.
3.1.15 Offset_3C Interrupt Line Register
This register provides the interrupt line routing information specific to the
μ
PD72873, the NEC’s implementation of
the 1394 OHCI specification.
Bits
R/W
Description
7-0
R/W
Default value of 00H. It specifies which input of the host system interrupt controller the
interrupt pin of the
μ
PD72873 is connected to.