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參數(shù)資料
| 型號： | UPD750004GBA-XXX-3BS-MTX |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 14/86頁 |
| 文件大?。?/td> | 626K |
| 代理商： | UPD750004GBA-XXX-3BS-MTX |
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PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)
19
Data Sheet U10738EJ3V2DS
Fig. 5-3
Program Memory Map (in
PD750008)
Note Can be used only in the Mk
ΙΙ mode.
Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with
only the 8 low-order bits of the PC changed.
0000H
Address
0002H MBE RBE
0
INTBT/INT4
(high-order 5 bits)
start address
0004H MBE RBE
0
INT0
(high-order 5 bits)
start address
0006H MBE RBE
0
INT1
(high-order 5 bits)
start address
0008H MBE RBE
0
INTCSI
(high-order 5 bits)
start address
000AH MBE RBE
0
INTT0
(high-order 5 bits)
start address
0020H
007FH
0080H
07FFH
0800H
MBE RBE
0
Internal reset start address
(high-order 5 bits)
0FFFH
1000H
1FFFH
GETI instruction reference table
000CH MBE RBE
0
INTT1
(high-order 5 bits)
start address
(low-order 8 bits)
CALLF
!faddr
instruction
entry
address
BRCB !caddr
instruction
branch
address
Branch address
of BR BCXA, BR
BCDE, BR !addr,
BRA !addr1 or
CALLA !addr1Note
instruction
CALL !addr
instruction
subroutine entry
address
BR $addr
instruction relative
branch address
-15 to -1,
+2 to +16
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
BRCB !caddr
instruction
branch
address
765
0
Internal reset start address
INTBT/INT4
INT0
INT1
INTCSI
INTT0
INTT1
start address
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