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參數(shù)資料
| 型號(hào)： | UPD750004GBA-XXX-3BS-MTX |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 61/86頁(yè) |
| 文件大小： | 626K |
| 代理商： | UPD750004GBA-XXX-3BS-MTX |
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PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)
62
Data Sheet U10738EJ3V2DS
SBI mode (SCK: Internal clock output (master)): (TA = -40 to +85
°C, VDD = 2.2 to 5.5 V)
Note RL is the resistance of the SB0/SB1 output line load, while CL is the capacitance.
SBI mode (SCK: External clock input (slave)): (TA = -40 to +85
°C, VDD = 2.2 to 5.5 V)
Note RL is the resistance of the SB0/SB1 output line load, while CL is the capacitance.
Typ.
Max.
250
1000
Unit
ns
Min.
1300
3800
tKCY3/2 - 50
tKCY3/2 - 150
150
500
tKCY3/2
0
tKCY3
Conditions
VDD = 2.7 to 5.5 V
RL = 1 k
VDD = 2.7 to 5.5 V
CL = 100 pFNote
Symbol
tKCY3
tKL3,
tKH3
tSIK3
tKSI3
tKSO3
tKSB
tSBK
tSBL
tSBH
Parameter
SCK cycle time
SCK high/low level
width
SB0/SB1 setup time
(referred to SCK
↑)
SB0/SB1 hold time
(referred to SCK
↑)
Delay time from SCK
↓
to SB0/SB1 output
From SCK
↑ to SB0/SB1↓
From SB0/SB1
↓ to SCK↓
SB0/SB1 low level width
SB0/SB1 high level
width
Typ.
Max.
300
1000
Unit
ns
Min.
800
3200
400
1600
100
150
tKCY4/2
0
tKCY4
Conditions
VDD = 2.7 to 5.5 V
RL = 1 k
VDD = 2.7 to 5.5 V
CL = 100 pFNote
Symbol
tKCY4
tKL4,
tKH4
tSIK4
tKSI4
tKSO4
tKSB
tSBK
tSBL
tSBH
Parameter
SCK cycle time
SCK high/low level
width
SB0/SB1 setup time
(referred to SCK
↑)
SB0/SB1 hold time
(referred to SCK
↑)
Delay time from SCK
↓
to SB0/SB1 output
From SCK
↑ to SB0/SB1↓
From SB0/SB1
↓ to SCK↓
SB0/SB1 low level width
SB0/SB1 high level
width
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