參數(shù)資料
型號(hào)： UPD75068A
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述： 4位單片機(jī)
文件頁(yè)數(shù)： 22/68頁(yè)
文件大?。?/td> 640K
代理商： UPD75068A
22
μ
PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
5.5 Watch Timer
The
μ
PD75068 has an on-chip 1-ch watch timer. The watch timer has the following functions:
Sets the test flag (IRQW) with a 0.5-sec interval. The standby mode can be released by IRQW.
The 0.5-second interval can be generated from either the main system clock or subsystem clock.
The time interval can be made 128 times faster (3.91 ms) by selecting the fast mode. This is convenient
for program debugging, testing, etc.
Any of the frequencies 2.048 kHz, 4.096 kHz, and 32.768 kHz can be output to the P23/BUZ pin. This
can be used for beep and system clock frequency trimming.
The frequency divider circuit can be cleared so that a zero-second start of the watch can be made.
Figure 5-4. Watch Timer Block Diagram
Remark
( ) is for f
X
= 4.194304 MHz, f
XT
= 32.768 kHz.
P23/BUZ
Internal bus
8
Selector
From the
clock
generator
X
128
(32.768 kHz)
f
XT
(32.768 kHz)
Selector
Frequency divider
Selector
INTW
IRQW
set signal
2 Hz
0.5 sec
WM7
0
WM5 WM4 WM3 WM2 WM1 WM0
P23 output
latch
Bit 2 of PMGB
PORT2.3
Output buffer
Clear signal
f
W
(32.768 kHz)
Bit test instruction
Port 2 input/
output mode
WM
(4 kHz)2 kHz)
f
w
2
3
f
w
2
7
(256 Hz: 3.91 ms)
f
w
2
14
f
w
2
4
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