參數(shù)資料
型號(hào)： UPD75068A
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述： 4位單片機(jī)
文件頁(yè)數(shù)： 46/68頁(yè)
文件大小： 640K
代理商： UPD75068A
46
μ
PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
AC Characteristics (T
a
= –40 to +85
°
C, V
DD
= 2.7 to 6.0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
CPU clock
cycle time
Note
1
( minimum
instruction
execution time =
1 machine cycle )
Operating on main
system clock
V
DD
= 4.5 to 6.0 V
0.95
64
μ
s
3.8
64
μ
s
Operating on subsystem clock
114
122
125
μ
s
TI0 input
frequency
V
DD
= 4.5 to 6.0 V
0
1
MHz
f
TI
0
275
kHz
TI0 input high and
low level width
V
DD
= 4.5 to 6.0 V
0.48
μ
s
1.8
μ
s
Interrupt input high
and low level width
INT0
Note2
μ
s
INT1, INT2, INT4
10
μ
s
KR0 to KR3
10
μ
s
RESET low level
width
t
RSL
10
μ
s
Capacitance (T
a
= 25
°
C, V
DD
= 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
C
I
f = 1 MHz
Unmeasured pins returned to 0 V.
15
pF
Output capacitance
C
O
15
pF
I/O capacitance
C
IO
15
pF
t
CY
t
TIH
,
t
TIL
t
INTH
,
t
INTL
t
CY
vs V
DD
(Operating on Main System Clock)
C
C
s
Supply Voltage V
DD
[V]
0
1
2
3
4
5
6
0.5
1
2
3
4
5
60
70
6
Operation
guarantee range
Notes 1.
The cycle time (minimum instruction
execution time) of the CPU clock (
Φ
) is
determined by the oscillation frequency of
the connected resonator, the system clock
control register (SCC), and the processor
clock control register (PCC). The figure at
the right indicates the cycle time t
CY
versus
supply voltage V
DD
characteristic with the
main system clock operating.
2.
2t
CY
or 128/f
X
is set by setting the interrupt
mode register (IM0).
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