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參數(shù)資料
| 型號(hào)： | UPD75068A |
| 廠(chǎng)商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機(jī) |
| 文件頁(yè)數(shù)： | 42/68頁(yè) |
| 文件大小： | 640K |
| 代理商： | UPD75068A |
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42
μ
PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Subsystem Clock Oscillator Characteristics (T
a
= –40 to +85
°
C, V
DD
= 2.7 to 6.0 V)
Recommended
Constant
MIN.
TYP.
MAX.
Unit
Resonator
Parameter
Conditions
Oscillation
frequency (f
XT
)
Note1
V
DD
= 4.5
to 6.0 V
Oscillation
stabilization
time
Note2
XT1 input
frequency (f
XT
)
Note1
32
100
kHz
XT1 input high-/
low-level width
(t
XTH
,t
XTL
)
Notes 1.
The oscillation frequency indicates characteristics of the oscillator only. For the instruction execution
time, refer to the AC characteristics.
2.
The oscillation stabilization time is the required time for oscillation to stabilize after the voltage level
of V
DD
reaches the MIN. value of the oscillation voltage range.
Caution
If the subsystem clock oscillator is used, the wiring in the area indicated with broken lines in the
recommended constant illustration should be routed observing the points described below to avoid
influence of wiring capacitance, etc.
Route as short as possible.
Do not cross the wires.
Route the wires away from lines where changing high current flows.
Make the connecting point of the capacitors in the oscillation circuit to have always the same potential
as V
SS
. Do not route the connecting point to another ground pattern on the board where high current
flows.
Do not use the oscillator as a signal source of other circuits.
Especially when using the subsystem clock, be sure to design wiring so as to minimize noise. The
subsystem clock oscillator uses a low-amplification circuit to minimize power dissipation. As a result,
malfunctions due to noise are more liable to occur than with the main system clock oscillator.
32
32.768
50
kHz
1.0
2
s
10
s
5
15
μ
s
Crystal
resonator
External
clock
XT1
XT2
C4
C3
V
SS
R
XT1
XT2
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