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參數(shù)資料
| 型號： | UPD75208CW |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機 |
| 文件頁數(shù)： | 8/62頁 |
| 文件大小： | 497K |
| 代理商： | UPD75208CW |
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8
μ
PD75208
Segment output high voltage output.
Static output also possible.
Pin Name
I/O
Dual-
Function Pin
Input / Output
Circuit Type
*
Function
After Reset
Digit/segment output dual-function
high-voltage high-current output.
Extra pins can be used as PORTH.
Digit output high-voltage high-current
output.
FIP controller/
driver output
pins.
Pull-down
resistor can be
incorporated in
bit units (mask
option).
T0 to T9
Digit/segment output dual-function
high-voltage high-current output.
Static output also possible.
T10 to T13
T14/S11,
T15/S10
S9
Output
–––
PH3 to PH0
–––
Low
level
(with an on-
chip pull-
down
resistor ) or
high
impedance
(without a
pull-down
resistor)
I
3.2
NON-PORT PINS
*
Schmitt trigger inputs are circled.
B
F
Segment high-voltage output.
S0 to S8
High
impedance
PPO
Output
Input
–––
Timer/pulse generator pulse output.
External event pulse input for timer/event counter.
P13
Serial clock input/output.
TI0
SCK
Serial data output pin or serial data input/output.
Serial data input or normal input.
Edge-detected vectored interrupt input (rising and falling
edge detection).
INT0
INT1
SO
SI
INT4
Input/output
Input
Input
Input
P01
P02
P03
P00
P10
P11
Edge-detected vectored interrupt input with noise
eliminate function (detection edge selection possible).
Edge-detected testable input (rising edge detection).
Fixed frequency output (for buzzer or system clock
trimming).
Crystal/ceramic connect pin for main system clock
oscillation.
External clock input to X1 and its inverted clock input to
X2.
Crystal connect pin for subsystem clock oscillation.
External clock input to XT1 and XT2 open.
INT2
Input
Input/output
P12
P23
BUZ
X1, X2
XT1
Input
Input
FIP controller/driver output buffer power supply.
FIP controller/driver pull-down resistor connect pin.
GND potential.
XT2
–––
–––
–––
System reset input (low level active).
RESET
V
PRE
Input
–––
Positive power supply.
V
LOAD
V
DD
–––
–––
–––
V
SS
D
Input
B
Input
G
Input
B
B
B
B
Input
E
I
I
Input/output
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