參數資料
型號: UPD75312A
廠商: NEC Corp.
英文描述: 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述: 4位單片機
文件頁數: 54/62頁
文件大?。?/td> 577K
代理商: UPD75312A
μ
PD75312(A), 75316(A)
54
LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE
(T
a
= –40 to +85
°
C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Data Retention Supply
Voltage
Data Retention Supply
Current*
1
Release Signal Set Time
V
DDDR
2.0
6.0
V
I
DDDR
V
DDDR
= 2.0 V
0.1
10
μ
A
t
SREL
0
μ
s
ms
ms
Oscillation Stabilization
Wait Time*
2
t
WAIT
Released by RESET
Released by interrupt
2
17
/f
X
*3
*1: Does not include current flowing through internal pull-up resistor
2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent
unstable operation when oscillation is started.
3: Depends on the setting of the basic interval timer mode register (BTM) as follows:
BTM3
BTM2
0
0
1
BTM1
0
1
0
BTM0
0
1
1
WAIT time ( ): f
X
= 4.19 MHz
2
20
/f
X
(approx. 250 ms)
2
17
/f
X
(approx. 31.3 ms)
2
15
/f
X
(approx. 7.82 ms)
2
13
/f
X
(approx. 1.95 ms)
1
1
1
DATA RETENTION TIMING (releasing STOP mode by RESET)
DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)
STOP mode
Data retention mode
STOP instruction
execution
V
DD
RESET
V
DDDR
t
SREL
t
WAIT
Operation
mode
Internal reset operation
HALT mode
STOP mode
Data retention mode
STOP instruction execution
V
DD
V
DDDR
t
SREL
t
WAIT
Operation
mode
HALT mode
Standby release signal
(interrupt request)
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