參數(shù)資料
型號(hào)： UPD75312BGC
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述： 4位單片機(jī)
文件頁(yè)數(shù)： 18/77頁(yè)
文件大小： 587K
代理商： UPD75312BGC
18
μ
PD75312B, 75316B
5.2
CLOCK GENERATOR
The operation of the clock generator circuit is determined by the processor clock control register (PCC) and the
system clock control register (SCC).
There are two kinds of clocks; the main system clock and the subsystem clock.
It is also possible to change the instruction execution time.
0.95
μ
s/1.91
μ
s/15.3
μ
s (main system clock: @ 4.19 MHz)
122
μ
s (sub-system clock: @ 32.768 kHz)
Fig. 5-1 Clock Generator Block Diagram
f
X
:
f
XT
:
Φ
:
PCC:
SCC:
Remarks
Main system clock frequency
Subsystem clock frequency
CPU clock
Processor clock control register
System clock control register
1.
*
indicates instruction execution.
2.
Φ
one clock cycle (t
CY
) is one machine cycle instruction. For t
CY,
refer to AC characteristics in "
11
ELECTRICAL SPECIFICATIONS
."
Subsystem
Clock Oscil-
lator
XT1
XT2
X1
X2
V
DD
V
DD
f
XT
f
X
LCD Controller/
Driver
Watch Timer
Basic Interval Timer (BT)
Timer/Event Counter
Serial Interface
Watch Timer
LCD Controller/Driver
INT0 Noise Eliminator
Clock Output Circuit
1/8 to 1/4096
Frequency Divider
1/2
S
S
Frequency
Divider
1/4
CPU
INT0 Noise
Eliminator
Clock Output
Circuit
HALT F/F
S
Wait Release Signal from BT
RESET Signal
Standby Release Signal from
Interrupt Control Circuit
STOP F/F
Q
S
R
PCC2,
PCC3
Clear
Oscil-
lation
Stop
WM. 3
SCC
PCC
4
I
Main System
Clock Oscil-
lator
R
Q
PCC0
PCC1
PCC2
PCC3
SCC3
SCC0
HALT
*
STOP
*
1/16
Φ
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