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參數資料
| 型號： | UPD75312BGC |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機 |
| 文件頁數： | 9/77頁 |
| 文件大小： | 587K |
| 代理商： | UPD75312BGC |
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9
μ
PD75312B, 75316B
SYNC
*4
X1, X2
XT1
XT2
RESET
IC
V
DD
V
SS
Function
External event pulse input pin to timer/event counter
Timer/event counter output pin
Clock output pin
Fixed frequency output pin (for buzzer or system clock
trimming)
Serial clock input/output pin
Serial data output pin
Serial bus input/output pin
Serial data input pin
Serial bus input/output pin
Edge detection vectored interrupt input pin (both rising
edge and falling edge detection effective)
Edge detection vectored
interrupt input pin (detection
edge selectable)
Segment signal output pin
Segment signal output pin
Common signal output pin
LCD drive power supply pin
On-chip split resistor (mask option)
External split resistor cut output pin
External expansion driver drive clock output pin
External expansion driver synchronization clock output
pin
Main system clock oscillation crystal/ceramic connection
pin. For external clock, the external clock signal is input
to X1 and the inverted phase is input to X2.
Subsystem clock oscillation crystal connection pin. For
external clock, the external clock signal is input to XT1
and XT2 is opened. XT1 can be used as a 1-bit input
(test) pin.
System reset input pin
Internally Connected. Directly connected to V
DD
.
Positive power supply pin
GND potential pin
Pin Name
TI0
PTO0
PCL
BUZ
SCK
SO/SB0
SI/SB1
INT4
INT0
S0 to S23
S24 to S31
COM0 to COM3
V
LC0
to V
LC2
BIAS
LCDCL
*4
Dual-
Function Pin
P13
P20
P22
P23
P01
P02
P03
P00
P10
—
BP0 to BP7
—
—
—
P30
P31
––
—
—
—
—
—
—
Clocked
Asynchronous
Asynchronous
Input/Output
Input
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input
Output
Output
Output
—
Output
Input/output
Input/output
Input
Input
—
Input
—
—
—
Reset
Input
Input
Input
Input
Input
Input
Input
Input
*2
*2
*2
—
*3
Input
Input
—
––
—
—
—
—
INT1
P11
INT2
Edge detection testable input
pin (rising edge detection)
I/O Circuit
Type
*1
B - C
E - B
E - B
E - B
F - A
F - B
M - C
B
G - A
G - C
G - B
—
—
E - B
E - B
––
––
B
—
—
—
KR0 to KR3
Input/output
P60 to P63
Parallel falling edge detection testable input pin
Input
F - A
Input
KR4 to KR7
Input/output
P70 to P73
Parallel falling edge detection testable input pin
F - A
3.2
NON-PORT PINS
Input
Input
P12
Input
Input
B - C
B - C
* 1.
* 2.
Display outputs are selected with V
LCX
shown below as the input source.
S0 to S31: V
LC1
, COM0 to COM2: V
LC2
, COM3: V
LC0
However, the level of each display output depends on the display output and VLCX external circuit.
* 3.
On-chip split resistor………Low level
No on-chip split resistor… High-impedance
* 4.
Pins provided for system expansion. Currently, only used as P30 and P31 pins.
: Schmitt triggered input
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