參數(shù)資料
型號(hào)： UPD753204GT
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 4位單晶片微控制器
文件頁(yè)數(shù)： 14/80頁(yè)
文件大小： 577K
代理商： UPD753204GT
14
μ
PD753204, 753206, 753208
4
SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE
4.1 Difference Between Mk I and Mk II Modes
The CPU of the
μ
PD753208 has the following two modes: Mk I and Mk II, either of which can be selected.
The mode can be switched by bit 3 of the Stack Bank Select register (SBS).
Mk I mode:
Upward compatible with the
μ
PD75308B. Can be used in the 75XL CPU with a ROM
capacity of up to 16 Kbytes.
Incompatible with
μ
PD75308B. Can be used in all the 75XL CPU including those products
whose ROM capacity is more than 16 Kbytes.
Mk II mode:
Table 4-1. Differences between Mk I Mode and Mk II Mode
Mk I mode
Mk II mode
Number of stack bytes
for subroutine instructions
2 bytes
3 bytes
BRA ! addr1 instruction
CALLA ! addr1 instruction
Not available
Available
CALL ! addr instruction
3 machine cycles
4 machine cycles
CALLF ! faddr instruction
2 machine cycles
3 machine cycles
Caution
The MkII mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series.
Software compatibility with products whose program memory exceeds 16 Kbytes can be raised
by using this mode.
When the MkII mode is selected, the number of stack bytes increases by one byte per stack
during subroutine call instruction execution compared with the MkI mode. When the !faddr
instruction is used, the length of each machine cycle increases by 1 machine cycle. Therefore,
if RAM efficiency or processing speed is emphasized over software compatibility, use of the MkI
mode is recommended.
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