57
μ
PD753204, 753206, 753208
SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (T
A
= –40 to +85C, V
DD
= 1.8 to 5.5 V)
Resonator
Recommended constant
Parameter
Test conditions
MIN.
TYP.
MAX.
Unit
Ceramic
resonator
Oscillator
frequency (f
X
)
Note 1
1.0
6.0
Note 2
MHz
Oscillation
stabilization time
Note 3
After V
DD
reaches oscil-
lation voltage range MIN.
4
ms
Crystal
resonator
Oscillator
frequency (f
X
)
Note 1
1.0
6.0
Note 2
MHz
Oscillation
stabilization time
Note 3
V
DD
= 4.5 to 5.5 V
10
ms
30
External
clock
X1 input
frequency (f
X
)
Note 1
1.0
6.0
Note 2
MHz
X1 input
high/low level width
(t
XH
, t
XL
)
83.3
500
ns
Notes 1.
The oscillator frequency and X1 input frequency indicate characteristics of the oscillator only. For the
instruction execution time, refer to the AC characteristics.
2.
When the oscillator frequency is 4.19 MHz < fx
≤
6.0 MHz, setting the processor clock control register
(PCC) to 0011 results in 1 machine cycle being less than the required 0.95
μ
s. Therefore, set PCC
to a value other than 0011.
3.
The oscillation stabilization time is necessary for oscillation to stabilize after applying V
DD
or releasing
the STOP mode.
Caution
When using the system clock oscillator, wiring in the area enclosed with the dotted line should
be carried out as follows to avoid an adverse effect from wiring capacitance.
Wiring should be as short as possible.
Wiring should not cross other signal lines.
Wiring should not be placed close to a varying high current.
The potential of the oscillator capacitor ground should be the same as V
DD
.
Do not ground it to the ground pattern in which a high current flows.
Do not fetch a signal from the oscillator.
X2
X1
C1
C2
V
DD
X2
X1
C1
C2
V
DD
X1
X2