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參數(shù)資料
| 型號： | UPD753204GT |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 4位單晶片微控制器 |
| 文件頁數(shù)： | 9/80頁 |
| 文件大小： | 577K |
| 代理商： | UPD753204GT |
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9
μ
PD753204, 753206, 753208
3.2 Non-Port Pins (1/2)
Pin Name
Input/Output
Alternate
Function
Function
After Reset
I/O Circuit
TYPE
Note 1
TI0
Input
P13
Inputs external event pulses to the timer/event
counter.
Input
(B)-C
PTO0
Output
P20
Timer/event counter output
Input
E-B
PTO1
P21
Timer counter output
PTO2
P22/PCL
PCL
P22/PTO2
Clock output
BUZ
P23
Optional frequency output (for buzzer output
or system clock trimming)
SCK
Input/Output
P01
Serial clock input/output
Input
(F)-A
SO/SB0
P02
Serial data output
Serial data bus input/output
(F)-B
SI/SB1
P03
Serial data input
Serial data bus input/output
(M)-C
INT4
Input
P00
Edge detection vectored interrupt input (both
rising edge and falling edge detection)
Input
(B)
INT0
Input
P10
Input
(B)-C
KR0 to KR3
Input/Output
P60 to P63
Falling edge detection testable input
Input
(F)-A
S12 to S15
Output
–
Segment signal output
Note 2
G-A
S16 to S19
Output
P93 to P90
Segment signal output
Input
H
S20 to S23
Output
P83 to P80
Segment signal output
Input
H
COM0 to COM3
Output
–
Common signal output
Note 2
G-B
V
LC0
to V
LC2
–
–
LCD drive power
On-chip split resistor is enable (mask option).
–
–
BIAS
Output
–
Output for external split resistor disconnect
Note 3
–
LCDCL
Note 4
Input/Output
P30
Clock output for externally expanded driver
Input
E-B
SYNC
Note 4
Input/Output
P31
Clock output for externally expanded driver sync
Input
E-B
Notes 1.
Characters in parentheses indicate the Schmitt trigger input.
2.
Each display output selects the following VLCX as input source.
S12 to S15: V
LC1
, COM0 to COM2: V
LC2
, COM3: V
LC0
.
3.
When a split resistor is contained ....... Low level
When no split resistor is contained ......High-impedance
4.
These pins are provided for future system expansion.
At present, these pins are used only as pins P30 and P31.
Edge detection vectored
interrupt input (detection
edge can be selected).
Noise elimination circuit
can be specified.
With clock elimination
circuit/asynchronous
selectable
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