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參數(shù)資料
| 型號： | UPD75512A |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機 |
| 文件頁數(shù)： | 34/64頁 |
| 文件大?。?/td> | 494K |
| 代理商： | UPD75512A |
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μ
PD75512(A)
34
8. RESET FUNCTIONS
When the
RESET
signal is input, the
μ
PD75512(A) is reset and each hardware is initialized as indicated in
Table 8-1. Fig. 8-1 shows the reset operation timing.
RESET input
Wait
(31.3ms/4.19MHz)
Operation mode
or standby mode
HALT mode
Operation mode
Internal reset operation
Fig. 8-1 Reset Operation by RESET Input
Table 8-1 Status of Each Hardware after Reset (1/2)
Hardware
RESET Input in Standby Mode
RESET Input during Operation
Program Counter (PC)
The contents of the lower 6 bits
of address 0000H of the program
memory are set to PC13-8, and
the contents of address 0001H
are set to PC7-0.
Same as left
PSW
Carry Flag (CY)
Retained
Undefined
Skip Flag (SK0-2)
0
0
Interrupt Status Flag (IST0, 1)
0
0
Bank Enable Flag (MBE, RBE)
The contents of bit 6 of address
0000H of the program memory
are set to RBE and those of bit 7
are set to MBE.
Undefined
Same as left
Stack Pointer (SP)
Undefined
Data Memory (RAM)
General-Purpose Register
(X, A, H, L, D, E, B, C)
Retained *
Retained
Undefined
Undefined
Bank Selection Register (MBS, RBS)
0, 0
0, 0
Basic Interval
Timer
Counter (BT)
Undefined
Undefined
Timer/Event
Counter
Counter (T0)
0
0
Modulo Register
(TMOD0)
Mode Register (TM0)
FFH
FFH
0
0
TOE0, TOUT F/F
0, 0
0, 0
Mode Register (BTM)
0
0
Timer/Pulse
Generator
Modulo Register
0
Mode Register
0
Mode Register (WM)
0
Watch Timer
0
Retained
Retained
*
: Data of address 0F8H to 0FDH of the data memory becomes undefined when a
RESET
signal is input.
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