參數(shù)資料
型號(hào)： UPD7566ACSA
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述： 4位單片機(jī)
文件頁數(shù)： 12/58頁
文件大?。?/td> 471K
代理商： UPD7566ACSA
μ
PD7566A, 7566A(A)
12
1.7 I/O PORT OPERATIONS
(1) P00, P01 (Port 0)
Port 0 is a 2-bit input port and consists of pins P00 and P01. These pins are multiplexed, and P00 can
also input count clocks or testable signal (INT0), while P01 is used, when so specified by a mask option,
to input a reference voltage (Vref) to the internal comparator.
To input a count clock from P00, set bits 2 and 1 (CM2 and 1) for the clock mode register to “01” (see
2.10, Clock Control Circuit).
To allow P00 to serve as INT0, set the SM3 flag to 1.
Whether P01 is used to input a reference voltage (Vref) to the comparator is specified by a mask option.
In this case, the port function for the P01 pin cannot be used. The data on P00 and P01 can be loaded to
the lower 2 bits (A0 and A1) of the accumulator at any time, by executing a port input instruction (IPL, L
= 0).
(2) P10/Cin 0 to P13/Cin 3 (Port 1)
Port 1 is a 4-bit input port consisting of these four pins, which can also be used to input analog voltages
to the comparator, when so specified by mask options.
To input analog voltages through Port 1, a comparator must be connected to each bit of the port by
a mask option, and a port input instruction (IPL, L = 1) must be executed.
The analog voltage input through these pins to the comparator is always compared with a reference
voltage input through the Vref pin. It takes up to 3 machine cycles to accomplish this comparison.
Therefore, to change the voltage applied to the Vref pin by port output to form an A/D converter by using
a resistor ladder, wait for 3 machine cycles after executing a port output (OPL) instruction. Then carry out
an input (IPL, L = 1) instruction to obtain the result of the comparison.
If the output instruction is executed during a 3 machine cycle period that precedes the IPL instruction
(L = 1), which inputs the comparison result, the comparator accuracy may be degraded. For this reason,
do not execute the OPL instruction during 3 machine cycles immediately before the IPL instruction is
executed.
Example: LHLI
0AH
;
;
L = 10
Port 10 output (Vref is changed)
OPL
NOP
NOP
LHLI
IPL
1
;
;
L = 1
Input of comparison result
(3) P80 to P82 (Port 8), and P90 to P91 (Port 9)
Pins 80 to P82 constitute a 3-bit output port with output latch, Port 8, while P90 to P91 form a 2-bit output
port with output latch, Port 9.
When a port output instruction (OPL, L = 8, or L = 9) is executed, the contents of the accumulator are
latched on the output latches, and, at the same time, output to these ports.
Each bit in Ports 8 and 9 can be set or reset by SPBL or RPBL instruction.
Two output modes can be selected for Ports 8 and 9 by a mask option: CMOS (push-pull) or N-channel
open-drain mode.
The N-channel open-drain output mode is useful for interfacing a circuit operating on a supply voltage
different from that to the microcomputer, because the output buffer in this mode can withstand an applied
9V.
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