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參數(shù)資料
| 型號： | UPD7566ACSA |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機 |
| 文件頁數(shù)： | 23/58頁 |
| 文件大?。?/td> | 471K |
| 代理商： | UPD7566ACSA |
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μ
PD7566A, 7566A(A)
23
3. STANDBY FUNCTIONS
The
μ
PD7566A can be set in two standby modes (STOP and HALT), in which the power dissipation for the
microcomputer can be reduced while the program stands by. The STOP mode is set by a STOP instruction, while
the HALT mode is set by a HALT Instruction. In the STOP mode, the supply of all the clocks is stopped, but the supply
of only the CPU clock is stopped in the HALT mode. When the HALT mode is set, program execution is stopped,
but the contents of all the registers and data memory, immediately before the HALT mode has been set, are retained.
The timer/event counter can operate even in the HALT mode.
The STOP mode is released only by the input of the RESET signal. The HALT mode can be released by setting
either or both the test request flags (INTT RQF and INT0 RQF), or by inputting the RESET signal. Therefore, the
standby mode cannot be set, even when the STOP or HALT instruction is executed while one of the test request
flags is set. To set the standby mode, when it is possible that one of the test request flags is set, execute an SKI
instruction in advance to reset the test request flag.
3.1 STOP MODE
The STOP mode can be set any time by executing the STOP instruction, unless either or both the test request
flags are set.
In this mode, the data memory contents are retained, but all other functions are stopped and become invalid,
except for the RESET signal, which is used to release the STOP mode. Consequently, the power dissipation for the
microcomputer is minimized.
Caution In the STOP mode, the CL1 pin is internally short-circuited to V
DD
(high level) to prevent the leakage
current from the ceramic oscillator.
3.2 HALT MODE
In this mode, only the 1/2 frequency divider for the system clock generator is stopped. Consequently, the supply
of system clock (CL) is not stopped and only the CPU clock () is stopped. The operation of the CPU, which calls
for the CPU clock, is therefore stopped.
However, the clock control circuit is not stopped. The clock control circuit can therefore input the CL signal
generated by the system clock generator and event pulses input from an external source through the P00 pin, can
supply both the clocks to the timer/event counter as count pulses (CPs). The timer/event counter can therefore
operate on both the count pulses and its operation will not be interrupted.
3.3 RELEASING STOP MODE BY USING RESET INPUT
When the RESET signal becomes high in the STOP mode, the HALT mode is set, and at the same time, ceramic
oscillation starts.
When the RESET signal goes low, the HALT mode is released followed by ordinary RESET operation. After that,
the CPU starts executing the program from address 0. The STOP mode is thus released.
The contents of the data memory are retained even while the mode is released, that the contents of registers
become undefined.
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