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參數(shù)資料
| 型號： | UPD7566ACSA |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機 |
| 文件頁數(shù)： | 22/58頁 |
| 文件大小： | 471K |
| 代理商： | UPD7566ACSA |
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μ
PD7566A, 7566A(A)
22
2.12 TEST CONTROL CIRCUIT
The test control circuit consists of two test flags, a flag called SM3, and a test request flag control circuit. The
test request flags, INT0 RQF and INTT RQF, are set by two kinds of test sources (external test input (INT0) and timer
overflow (INTT)). The SM3 flag determines whether or not inputting signals to the INT0 pin is enabled. The test
request flag control circuit checks the contents of the test request flags, when an SKI instruction is executed, and
resets the flags.
The SM3 flag is set by an OPL (L = 0FH) instruction (corresponding to A3). When this flag is 1, the INT0 input
is enabled.
The INT0 RQF flag is set when the rising edge is detected on the INT0 pin, and is reset by an SKI instruction.
The INTT RQF flag is set when an overflow occurs in the timer, and is reset by an SKI or TIMER instruction.
The signals output by the test request flags are used to release the HALT modes. If one of or both the flags were
to be set, the HALT modes are released.
When the RESET signal is input, both the test request flags and SM3 flag are reset. Therefore, INT0 input is
disabled as the initial condition after the RESET signal has been applied.
Fig. 2-13 Test Control Circuit
Note
indicates that an instruction has been executed.
Internal bus
SM3
INTT
INT0
NONSYNC
EDGE GATE
INTT
RQF
NONSYNC
EDGE GATE
INT0
RQF
S
R
S
R
Q
Q
HALT
RELEASE
TEST RQF
CONTROL
Note
Note
Note
OPL
SKI
TIMER
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