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參數(shù)資料
| 型號： | UPD75P316BGC-3B9 |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機(jī) |
| 文件頁數(shù)： | 20/46頁 |
| 文件大?。?/td> | 404K |
| 代理商： | UPD75P316BGC-3B9 |
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20
μ
PD75P316B
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85
°
C, V
DD
= 2.0 to 6.0 V)
RECOMENDED CONSTANT
UNIT
kHz
s
s
kHz
μ
s
RESONATOR
Crystal
resonator
External
clock
*
This is the time required for oscillation to stabilize after V
DD
reaches the MIN. value of the oscillation voltage
range.
Note
When the subsystem clock oscillator is used, the following should be noted concerning wiring in the area
in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc.
The wiring should be kept as short as possible.
No other signal lines should be crossed. Keep away from lines carrying a high fluctuating current.
The oscillator capacitor grounding point should always be at the same potential as V
DD
. Do not connect
to a ground pattern carrying a high current.
A signal should not be taken from the oscillator.
The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current,
and is more prone to misoperation due to noise than the main system clock oscillator. Particular care is
therefore required with the wiring method when the subsystem clock is used.
MAX.
35
2
10
100
15
TYP.
1.0
32.768
MIN.
32
32
5
TEST CONDITIONS
V
DD
=4.5 to 6.0 V
PARAMETER
Oscillation frequency
(f
XT
)
Oscillation stabilization
time
*
XT1 input frequency
(f
XT
)
XT1 input high-/low-
level width (t
XTH
, t
XTL
)
V
DD
XT2
XT1
C1
C2
R
XT2
XT1
Open
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