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參數(shù)資料
| 型號(hào)： | UPD77018GC |
| 廠商： | NEC Corp. |
| 英文描述： | CAT5E PATCH CABLES SNAGLESS,GREEN,10 FT |
| 中文描述： | 16位定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁數(shù)： | 17/60頁 |
| 文件大小： | 424K |
| 代理商： | UPD77018GC |
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17
μ
PD77015, 77017, 77018
2.2 Program Control Unit
Program control unit controls not only count up of program counter in normal operation, but loop, repeat,
branch, halt and interrupt.
In addition to loop stack of loop 4 level and program stack of 15 level, software stack can be used for multi-
loop and multi-interrupt/subroutine call.
The
μ
PD77017 has external 4 interruptions and internal 6 interruptions from peripheral, and specifies interrupt
enable or disable independently.
The HALT and STOP instructions cause the
μ
PD77017 to place in low power standby mode.
When the HALT instruction is executed, power consumption decreases. HALT mode is released by interrupt
input or hardware reset input. It takes several system clock to recover.
When the STOP instruction is executed, power consumption decreases. STOP mode is released by hardware
reset input. It takes a few ms to recover.
2.3 Operation Unit
Operation unit consists of the following five parts.
– 40 bits general register
×
8 for data load/store and input/output of operation data
– 16 bits
×
16 bits + 40 bits
→
40 bits multiply accumulator
– 40 bits Data ALU
– 40 bits barrel shifter
– SAC: shifter and count circuit.
Standard word length is 40 bits to make overflow check and adjustment easy, and to accumulate the result
of 16 bits
×
16 bits multiplication correctly.
2.3.1 General register (R0 to R7)
The
μ
PD77017 has eight 40 bits registers for operation input/output and load/store with memory. General
register consists of the following three parts.
– R0L to R7L (bit 15 to bit 0)
– R0H to R7H (bit 31 to bit 16)
– R0E to R7E (bit 39 to bit 32)
But each of RnL, RnH and RnE are treated as a register in the following conditions.
(1) General register used as 40 bits register
General registers are treated as 40 bits register, when they are used for the following aims.
(a) Operand for triminal operation (except for multiplier input)
(b) Operand for dyadic operation (except for multiplier and shift value)
(c) Operand for monadic operation (except for exponent instructions)
(d) Operand for operation
(e) Operand for conditional judge
(f)
Destination for load instruction (with sign extension and 0 clear)
Head room
0
0
1
31
32
39
S S S S S S S S
Result of multiplication among two's complement data
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| UPD77016 | 16 bits, Fixed-point Digital Signal Processor |
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