參數(shù)資料
型號(hào): UPD77213GJ-xxx-8EN
廠商: NEC Corp.
元件分類: 數(shù)字信號(hào)處理
英文描述: 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR
中文描述: 16位定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù): 49/74頁
文件大小: 467K
代理商: UPD77213GJ-XXX-8EN
Data Sheet U15203EJ3V0DS
49
μ
PD77210, 77213
AC Characteristics (T
A
=
20 to + 70
°
C, with IV
DD
and EV
DD
within recommended operating condition range)
Clock
Timing requirements
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
CLKIN cycle time
Note 1
t
cCX
62.5
ns
CLKIN high level width
t
wCXH
12.5
ns
CLKIN low level width
t
wCXL
12.5
ns
CLKIN rise/fall time
t
rfCX
5
ns
Internal clock cycle time
t
cC
Over 120 MHz(
μ
PD77210
only)
6.25
ns
requirements
Under 120 MHz
8.33
ns
PLL lock-up time
t
LPLL
300
μ
s
PLL lock frequency
Note 1
t
cPLL
When boot:P3
=
0
Note 2
120
160
MHz
When boot:P3
=
1
80
120
MHz
Notes 1.
The CLKIN cycle time must accord with the PLL lock frequency. It is therefore necessary to satisfy both
the CLKIN cycle time condition of 62.5 ns (MIN.) and the PLL lock frequency condition of a multiplied
frequency in the range of 80 to 160 MHz.
2.
In the
μ
PD77213, it can be set only when an external memory boot is being used.
Switching characteristics
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Internal clock cycle
Note
t
cC
t
cCX
÷
m
×
n
ns
CLKOUT cycle time
t
cCO
t
cC
ns
CLKOUT width
t
wCO
n = 1
t
cC
÷
2
ns
n
2
High level width
t
cC
÷
n
ns
Low level width
t
cC
t
cC
÷
n
ns
CLKOUT rise/fall time
t
rfCO
5
ns
CLKOUT delay time
t
dCO
6.25
ns
Note
m: Multiple ratio, n: Division ratio (PLL, divider)
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