參數(shù)資料
型號(hào)： UPD780024AGB-xxx-8EU
廠商： NEC Corp.
元件分類： 8位微控制器
英文描述： 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 8位單晶片微控制器
文件頁數(shù)： 33/96頁
文件大?。?/td> 661K
代理商： UPD780024AGB-XXX-8EU
33
μ
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Data Sheet U14042EJ4V0DS
6. INTERRUPT FUNCTIONS
A total of 20 interrupt sources are provided, divided into the following three types.
Non-maskable: 1
Maskable:
18
Software:
1
Table 6-1. Interrupt Source List
Interrupt
Type
Default
Priority
Note 1
Interrupt Source
Internal/
External
Name
Trigger
Non-
maskable
—
INTWDT
Watchdog timer overflow
(with watchdog timer mode 1 selected)
Internal
0004H
(A)
Maskable
0
INTWDT
Watchdog timer overflow
(with interval timer mode selected)
(B)
1
INTP0
Pin input edge detection
External
0006H
(C)
2
INTP1
0008H
3
INTP2
000AH
4
INTP3
000CH
5
INTSER0
Serial interface UART0 reception error
generation
Internal
000EH
(B)
6
INTSR0
End of serial interface UART0 reception
0010H
7
INTST0
End of serial interface UART0 transmission
0012H
8
INTCSI30
End of serial interface SIO30 transfer
0014H
9
INTCSI31
End of serial interface SIO31 transfer
[Only for
μ
PD780024A Subseries]
0016H
10
INTIIC0
End of serial interface IIC0 transfer
[Only for
μ
PD780024AY Subseries]
0018H
11
INTWTI
Reference time interval signal from watch timer
001AH
12
INTTM00
Match between TM0 and CR00
(when CR00 is specified as compare register)
Detection of TI01 valid edge
(when CR00 is specified as capture register)
001CH
13
INTTM01
Match between TM0 and CR01
(when CR01 is specified as compare register)
Detection of TI00 valid edge
(when CR01 is specified as capture register)
001EH
14
INTTM50
Match between TM50 and CR50
0020H
15
INTTM51
Match between TM51 and CR51
0022H
16
INTAD0
End of A/D conversion
0024H
17
INTWT
Watch timer overflow
0026H
18
INTKR
Port 4 falling edge detection
External
0028H
(D)
Software
—
BRK
BRK instruction execution
—
003EH
(E)
Notes 1.
The default priority is the priority when several maskable interrupt requests are generated at the same
time. 0 is the highest, and 18 is the lowest.
2.
Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1.
Remark
The watchdog timer interrupt (INTWDT) can be selected from a non-maskable interrupt or a maskable
interrupt (internal).
Basic
Configuration
Type
Note 2
Vector
Table
Address
相關(guān)PDF資料
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