參數(shù)資料
型號(hào)： UPD780024AGC-xxx-AB8
廠商： NEC Corp.
元件分類： 8位微控制器
英文描述： 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 8位單晶片微控制器
文件頁數(shù)： 67/96頁
文件大小： 661K
代理商： UPD780024AGC-XXX-AB8
67
μ
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Data Sheet U14042EJ4V0DS
(3) Serial Interface (T
A
=
–
40 to +85
°
C, V
DD
= 1.8 to 5.5 V)
(a) 3-wire serial I/O mode (SCK3n... Internal clock output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK3n
t
KCY1
4.0 V
≤
V
DD
≤
5.5 V
954
ns
cycle time
2.7 V
≤
V
DD
<
4.0 V
1600
ns
1.8 V
≤
V
DD
<
2.7 V
3200
ns
SCK3n high-/
t
KH1
, t
KL1
4.0 V
≤
V
DD
≤
5.5 V
t
KCY1
/2
–
50
ns
low-level width
1.8 V
≤
V
DD
<
4.0 V
t
KCY1
/2
–
100
ns
SI3n setup time
t
SIK1
4.0 V
≤
V
DD
≤
5.5 V
100
ns
(to SCK3n
↑
)
2.7 V
≤
V
DD
< 4.0 V
150
ns
1.8 V
≤
V
DD
<
2.7 V
300
ns
SI3n hold time
(from SCK3n
↑
)
t
KSI1
400
ns
Delay time from
SCK3n
↓
to SO3n
output
t
KSO1
C = 100 pF
Note
300
ns
Note
C is the load capacitance of the SCK3n and SO3n output lines.
(b) 3-wire serial I/O mode (SCK3n... External clock input)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK3n
4.0 V
≤
V
DD
≤
5.5 V
800
ns
cycle time
2.7 V
≤
V
DD
< 4.0 V
1600
ns
1.8 V
≤
V
DD
<
2.7 V
3200
ns
SCK3n high-/
t
KH2
, t
KL2
4.0 V
≤
V
DD
≤
5.5 V
400
ns
low-level width
2.7 V
≤
V
DD
< 4.0 V
800
ns
1.8 V
≤
V
DD
<
2.7 V
1600
ns
SI3n setup time
(to SCK3n
↑
)
t
SIK2
100
ns
SI3n hold time
(from SCK3n
↑
)
t
KSI2
400
ns
Delay time from
SCK3n
↓
to SO3n
output
t
KSO2
C = 100 pF
Note
300
ns
Note
C is the load capacitance of the SO3n output line.
Remark
Conventional products of
μ
PD780021A, 780022A, 780023A, 780024A: n = 0 or 1
μ
PD780021AY, 780022AY, 780023AY, 780024AY: n = 0
t
KCY2
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