參數(shù)資料
型號(hào)： UPD78322GJ-XXX-5BJ
元件分類(lèi)： 微控制器/微處理器
英文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP74
封裝： 20 X 20 MM, PLASTIC, QFP-74
文件頁(yè)數(shù)： 16/90頁(yè)
文件大?。?/td> 649K
代理商： UPD78322GJ-XXX-5BJ
21
PD78320, 78322
2.2.1
Control Register
The control registers carry out dedicated functions such as control of the program sequence, status and stack memory,
and modification of operand addressing. They consist of three 16-bit registers and one 8-bit register.
(1)
Program counter (PC)
This is a 16-bit register which holds the address information of the next program to be executed. It is normally
incremented according to the number of bytes of the instruction to be fetched. If an instruction with data branch is
executed, immediate data and the register content are set. RESET input sets and branches the data of 0000H and 0001H
reset vector tables in the PC.
(2)
Program status word (PSW)
This is a 16-bit register consisting of various flags which are set or reset by the result of instruction execution. Read/
write access is carried out in units of the higher 8 bits (PSWH) or lower 8 bits (PSWL). Each flag can be manipulated
using the bit manipulation instruction. If an interrupt request is made or BRK instruction is executed, data is automatically
saved in the stack and is recovered by RETI or RETB instruction.
All bits are reset to 0 by RESET input.
Figure 2-3. PSW Format
(a)
Interrupt priority level transition flag (LT)
This flag is used to control the interrupt priority. For normal operation of the interrupt control circuit, this bit must not
be manipulated by a program.
(b) Carry flag (CY)
If a carry is generated out of bit 7 or 15 as a result of the execution of an operation instruction or a borrow is generated
into bit 7 or 15, this flag is set to 1. In all other cases, this flag is reset to 0. This flag can be tested by the conditional
branch instruction.
When a bit manipulation instruction is executed, this flag functions as a bit accumulator.
(c)
Zero flag (Z)
When the operation result is zero, this flag is set to 1. In all other cases, this flag is reset to 0. This flag can be tested
by the conditional branch instruction.
(d) Sign flag (S)
When MSB of the operation result is “1”, this flag is set to 1. When the MSB is “0”, this flag is reset to 0. This flag
can be tested by the conditional branch instruction.
(e)
Parity/overflow flag (P/V)
Only when an overflow or underflow occurs as two’s complement during execution of an arithmetic operation
instruction, this flag is set to 1. In all other cases, it is reset to 0 (overflow flag operation).
If the bit number of the operation result set to 1 is even during execution of an logic operation instruction, this flag
is set to 1. If the bit number is odd, this flag is reset to 0 (parity flag operation).
This flag can be tested by the conditional branch instruction.
7
65432
10
UF
RBS2 RBS1 RBS0
0
PSWH
7654
3210
S
Z
RSS
AC
IE
P/V
LT
CY
PSWL
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