- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄300064 > UPD78322GJ-XXX-5BJ 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP74 PDF資料下載
參數(shù)資料
| 型號(hào)： | UPD78322GJ-XXX-5BJ |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP74 |
| 封裝： | 20 X 20 MM, PLASTIC, QFP-74 |
| 文件頁(yè)數(shù)： | 47/90頁(yè) |
| 文件大?。?/td> | 649K |
| 代理商： | UPD78322GJ-XXX-5BJ |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)當(dāng)前第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)
49
PD78320, 78322
7.
OPERATION AFTER RESET
If the RESET input pin is set to the low level, the system reset is applied and each hardware becomes as initialized status
(reset status). If RESET input becomes high level, the reset state is released and program execution is started. Initialize
the contents of various registers in the program as required.
Change the number of cycles for the programmable wait control register and the fetch cycle control register as required
in particular.
The RESET input pin is equipped with an analog delay noise eliminator to prevent malfunctioning due to noise.
Cautions 1. While RESET is active (low level), all pins remain high impedance (except WDTO, AVREF, AVDD, AVSS,
VDD, VSS, X1 and X2).
2. If RAM has been expanded externally, mount a pull-up resistor to the P90/RD and P91/WR pins. It is
possible that the P90/RD and P91/WR pins become high impedance resulting in an external RAM
contents corruption. In addition, signals may collide on the address/data bus, resulting in the
destruction of the input/output circuit.
Figure 7-1. Reset Signal Acknowledge
For reset operation upon power-up, secure the oscillation stabilization time of about 40 msec from power-up to reset
acknowledge as shown in Figure 7-2.
Figure 7-2. Reset Upon Power-Up
RESET Input
Analog
Delay
Eliminated
as Noise
Analog
Delay
Reset
Acknowl-
edged
Analog
Delay
Reset
Release
Oscillation
Stabilization
Time
Analog
Delay
Reset
Release
VDD
RESET
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD789132GS-XXX | 8-BIT, MROM, MICROCONTROLLER, PDSO30 |
| UPD789122UC-XXX-5A4 | 8-BIT, MROM, MICROCONTROLLER, PDSO30 |
| UPL4-NM-150 | INTERCONNECTION DEVICE |
| USB-AM-S-F-W-SM1-TR | 4 CONTACT(S), FEMALE, RIGHT ANGLE TELECOM AND DATACOM CONNECTOR, SURFACE MOUNT |
| USB-AM-S-S-B-SM1-TR | 4 CONTACT(S), FEMALE, RIGHT ANGLE TELECOM AND DATACOM CONNECTOR, SURFACE MOUNT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD78365AGF3B9 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| UPD784031GC-8BT-A | 制造商:Renesas Electronics Corporation 功能描述:MCU 8BIT/16BIT 78K4 CISC ROMLESS 3.3V/5V 80PQFP - Trays 制造商:Renesas Electronics 功能描述:16 制造商:Renesas Electronics 功能描述:16 Cut Tape |
| UPD784031GK-9EU-A | 制造商:Renesas Electronics Corporation 功能描述:16BIT K4 ROMLESS - Bulk |
| UPD784031YGC-8BT | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD784031YGC-8BT-A | 制造商:Renesas Electronics Corporation 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。