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參數(shù)資料
| 型號： | UPD78322GJ-XXX-5BJ |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP74 |
| 封裝： | 20 X 20 MM, PLASTIC, QFP-74 |
| 文件頁數(shù)： | 18/90頁 |
| 文件大?。?/td> | 649K |
| 代理商： | UPD78322GJ-XXX-5BJ |
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23
PD78320, 78322
(4)
CPU control word (CCW)
This is an 8-bit register consisting of CPU control related flags. It is mapped in the special function register area and
can be controlled by the software. All bits are reset to 0 by RESET input.
Figure 2-4. CCW Format
Table position flag (TPF)
This flag is used to specify the interrupt vector table area and the memory area used as CALLT instruction table area.
As TPF has been reset to 0 after application of RESET input, the 0000H to 007FH address is used as each table area.
The 8002H to 807FH address of the external memory area in place of 0002H to 007FH address can be used as each
table area by setting TPF to 1 using the software. The vector tables of the BRK instruction, operation code trap interrupt
and reset input are fixed to 003EH, 003CH and 0000H, respectively, and they are not affected by TPF.
2.2.2
General Registers
These are 128-byte registers mapped in the special area (FE80H to FEFFH) of the internal RAM space. They consist
of eight register banks. The general register in the bank consists of sixteen 8-bit registers.
Figure 2-5. General Register Memory Location
76
54321
0
00
0000
TPF
0
CCW
(FH)
RP7
(EH)
(DH)
RP6
(CH)
(BH)
RP5
(AH)
(9H)
RP4
(8H)
(7H)
RP3
(6H)
(5H)
RP2
(4H)
(3H)
RP1
(2H)
(1H)
RP0
(0H)
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
70 7
0
15
0
RBNK0
RBNK1
RBNK2
RBNK3
RBNK4
RBNK5
RBNK6
RBNK7
FEFFH
FE80H
8-Bit Processing
16-Bit Processing
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