μPD78F921x ONLY) User’s Manual U16994EJ6V0UD 164 (2) Analog input channel spe" />
參數(shù)資料
型號: UPD78F9212GR-JJG-A
廠商: Renesas Electronics America
文件頁數(shù): 75/175頁
文件大?。?/td> 0K
描述: MCU 8BIT 4KB FLASH MEM 16-SSOP
標準包裝: 1
系列: 78K0S/Kx1+
核心處理器: 78K0S
芯體尺寸: 8-位
速度: 10MHz
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-SSOP(0.173",4.40mm 寬)
包裝: 托盤
其它名稱: 972-1046
UPD78F9212GR-JJG-A-ND
CHAPTER 9 A/D CONVERTER (
μPD78F921x ONLY)
User’s Manual U16994EJ6V0UD
164
(2) Analog input channel specification register (ADS)
This register specifies the input port of the analog voltage to be A/D converted.
ADS can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 9-5. Format of Analog Input Channel Specification Register (ADS)
ADS0
ADS1
0
Analog input channel specification
ANI0
ANI1
ANI2
ANI3
ADS0
0
1
0
1
ADS1
0
1
0
1
2
3
4
5
6
7
ADS
Address: FF81H
After reset: 00H
R/W
Symbol
Caution
Be sure to clear bits 2 to 7 of ADS to 0.
(3) 10-bit A/D conversion result register (ADCR)
This register is a 16-bit register that stores the A/D conversion result. The higher six bits are fixed to 0. Each
time A/D conversion ends, the conversion result is loaded from the successive approximation register, and is
stored in ADCR in order starting from bit 1 of FF19H. FF19H indicates the higher 2 bits of the conversion result,
and FF18H indicates the lower 8 bits of the conversion result.
ADCR can be read by a 16-bit memory manipulation instruction.
Reset signal generation makes ADCR undefined.
Figure 9-6. Format of 10-bit A/D Conversion Result Register (ADCR)
Symbol
Address: FF18H, FF19H
After reset: Undefined
R
FF19H
FF18H
0
ADCR
Caution
When writing to the A/D converter mode register (ADM) and analog input channel
specification register (ADS), the contents of ADCR may become undefined.
Read the
conversion result following conversion completion before writing to ADM and ADS.
Using timing other than the above may cause an incorrect conversion result to be read.
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