參數(shù)資料
型號: UPD78F9212GR-JJG-A
廠商: Renesas Electronics America
文件頁數(shù): 9/175頁
文件大?。?/td> 0K
描述: MCU 8BIT 4KB FLASH MEM 16-SSOP
標準包裝: 1
系列: 78K0S/Kx1+
核心處理器: 78K0S
芯體尺寸: 8-位
速度: 10MHz
外圍設備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-SSOP(0.173",4.40mm 寬)
包裝: 托盤
其它名稱: 972-1046
UPD78F9212GR-JJG-A-ND
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
User’s Manual U16994EJ6V0UD
104
The external event counter counts the number of external clock pulses to be input to the TI000 pin with using 16-bit
timer counter 00 (TM00).
TM00 is incremented each time the valid edge specified by prescaler mode register 00 (PRM00) is input.
When the TM00 count value matches the 16-bit timer capture/compare register 000 (CR000) value, TM00 is
cleared to 0 and the interrupt request signal (INTTM000) is generated.
Input a value other than 0000H to CR000. (A count operation with a pulse cannot be carried out.)
The rising edge, the falling edge, or both edges can be selected using bits 4 and 5 (ES000 and ES010) of
prescaler mode register 00 (PRM00).
Because an operation is carried out only when the valid edge of the TI000 pin is detected twice after sampling with
the internal clock (fXP), noise with a short pulse width can be removed.
Figure 6-15. Control Register Settings in External Event Counter Mode (with Rising Edge Specified)
(a) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002
0/1
CRC001
0/1
CRC000
0
CRC00
CR000 used as compare register
(b) Prescaler mode register 00 (PRM00)
ES110
0/1
ES100
0/1
ES010
0
ES000
1
3
0
2
0
PRM001
1
PRM000
1
PRM00
Selects external clock.
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
(c) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003
1
TMC002
1
TMC001
0/1
OVF00
0
TMC00
Clears and starts on match between TM00 and CR000.
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter.
See the description of the respective control registers for details.
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