參數(shù)資料
型號： UPD78F9511GR-JJG-A
廠商： Renesas Electronics America
文件頁數(shù)： 37/175頁
文件大?。?/td> 0K
描述： MCU 8BIT SGL CHIP 16PIN
標準包裝： 400
系列： 78K0S/Kx1+
核心處理器： 78K0S
芯體尺寸： 8-位
速度： 10MHz
外圍設(shè)備： LVD，POR，PWM，WDT
輸入/輸出數(shù)： 13
程序存儲器容量： 2KB（2K x 8）
程序存儲器類型： 閃存
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 16-SSOP（0.173"，4.40mm 寬）
包裝： 托盤
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
User’s Manual U16994EJ6V0UD
129
(18) Edge detection
<1>
In the following cases, note with caution that the valid edge of the TI0n0 pin is detected.
(a) Immediately after a system reset, if a high level is input to the TI0n0 pin, the operation of 16-bit
timer counter 00 (TM00) is enabled
→ If the rising edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin,
a rising edge is detected immediately after the TM00 operation is enabled.
(b) If the TM00 operation is stopped while the TI0n0 pin is at high level, TM00 operation is then enabled
after a low level is input to the TI0n0 pin
→ If the falling edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin,
a falling edge is detected immediately after the TM00 operation is enabled.
(c) When the TM00 operation is stopped while the TI0n0 pin is at low level, TM00 operation is then
enabled after a high level is input to the TI0n0 pin
→ If the rising edge or both rising and falling edges are specified as the valid edge, of the TI0n0 pin,
a rising edge is detected immediately after the TM00 operation is enabled.
Remark
n = 0, 1
<2>
The sampling clock used to remove noise differs when the valid edge of TI000 is used as the count clock
and when it is used as a capture trigger. In the former case, the count clock is fXP, and in the latter case
the count clock is selected by prescaler mode register 00 (PRM00). The capture operation is not
performed until the valid edge is sampled and the valid level is detected twice, thus eliminating, noise
with a short pulse width.
(19) External event counter
<1>
The timing of the count start is after two valid edge detections.
<2>
When reading the external event counter count value, TM00 should be read.
(20) PPG output
<1>
Values in the following range should be set to CR000 and CR010:
0000H < CR010 < CR000
≤ FFFFH
<2>
The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of (CR010
setting value + 1)/(CR000 setting value + 1).
(21) STOP mode or system clock stop mode setting
Except when the valid edge of the TI000 pin is selected as the count clock, stop the timer operation before
setting STOP mode or system clock stop mode; otherwise the timer may malfunction when the system clock
starts.
(22) P21/TI010/TO00 pin
When using P21 as the input pin (TI010) of the valid edge, it cannot be used as a timer output pin (TO00).
When using P21 as the timer output pin (TO00), it cannot be used as the input pin (TI010) of the valid edge.
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參數(shù)描述
UPD78F9512GR-JJG-A 功能描述:MCU 8BIT SGL CHIP 16PIN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:78K0S/Kx1+ 標準包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設(shè)備:欠壓檢測/復(fù)位，LED，POR，PWM，WDT 輸入/輸出數(shù):16 程序存儲器容量:4KB（4K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND
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