μPD78F921x ONLY) User’s Manual U16994EJ6V0UD 163 Notes 3. Set the sampling ti" />
參數(shù)資料
型號(hào)： UPD78F9511GR-JJG-A
廠商： Renesas Electronics America
文件頁數(shù)： 74/175頁
文件大?。?/td> 0K
描述： MCU 8BIT SGL CHIP 16PIN
標(biāo)準(zhǔn)包裝： 400
系列： 78K0S/Kx1+
核心處理器： 78K0S
芯體尺寸： 8-位
速度： 10MHz
外圍設(shè)備： LVD，POR，PWM，WDT
輸入/輸出數(shù)： 13
程序存儲(chǔ)器容量： 2KB（2K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 16-SSOP（0.173"，4.40mm 寬）
包裝： 托盤
CHAPTER 9 A/D CONVERTER (
μPD78F921x ONLY)
User’s Manual U16994EJ6V0UD
163
Notes 3. Set the sampling time as follows.
VDD ≥ 4.5 V:
1.0
μs or more
VDD ≥ 4.0 V:
2.4
μs or more
VDD ≥ 2.85 V:
3.0
μs or more
VDD ≥ 2.7 V:
11.0
μs or more
4. Set the A/D conversion time as follows.
VDD ≥ 4.5 V:
3.0
μs or more and less than 100 μs
VDD ≥ 4.0 V:
4.8
μs or more and less than 100 μs
VDD ≥ 2.85 V:
6.0
μs or more and less than 100 μs
VDD ≥ 2.7 V:
14.0
μs or more and less than 100 μs
5.
Setting is prohibited because the values do not satisfy the condition of Notes 3 or 4.
6.
The operation of the comparator is controlled by ADCS and ADCE, and it takes 1
μs from
operation start to operation stabilization. Therefore, when ADCS is set to 1 after 1
μs or more
has elapsed from the time ADCE is set to 1, the conversion result at that time has priority over
the first conversion result. If the ADCS is set to 1 without waiting for 1
μs or longer, ignore the
first conversion data.
Table 9-2. Settings of ADCS and ADCE
ADCS
ADCE
A/D Conversion Operation
0
Stop status (DC power consumption path does not exist)
0
1
Conversion waiting mode (only comparator consumes power)
1
×
Conversion mode
Figure 9-4. Timing Chart When Comparator Is Used
ADCE
Comparator
ADCS
Conversion
operation
Conversion
operation
Conversion stopped
Conversion
waiting
Comparator operating
Note
Note The time from the rising of the ADCE bit to the rising of the ADCS bit must be 1
μs or longer to stabilize the
internal circuit.
Cautions 1. The above sampling time and conversion time do not include the clock frequency error.
Select the conversion time taking the clock frequency error into consideration (an error
margin maximum of
±5% when using the high-speed internal oscillator).
2. If a bit other than ADCS of ADM is manipulated while A/D conversion is stopped (ADCS = 0)
and then A/D conversion is started, execute two NOP instructions or an instruction
equivalent to two machine cycles, and set ADCS to 1.
3. A/D conversion must be stopped (ADCS = 0) before rewriting bits FR0 to FR2.
4. Be sure to clear bits 6, 2, and 1 to 0.
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