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參數(shù)資料
| 型號(hào)： | UPD78F9512GR-JJG-A |
| 廠商： | Renesas Electronics America |
| 文件頁(yè)數(shù)： | 113/175頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | MCU 8BIT SGL CHIP 16PIN |
| 標(biāo)準(zhǔn)包裝： | 400 |
| 系列： | 78K0S/Kx1+ |
| 核心處理器： | 78K0S |
| 芯體尺寸： | 8-位 |
| 速度： | 10MHz |
| 外圍設(shè)備： | LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 13 |
| 程序存儲(chǔ)器容量： | 4KB（4K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 16-SSOP（0.173"，4.40mm 寬） |
| 包裝： | 托盤 |
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CHAPTER 3 CPU ARCHITECTURE
User’s Manual U16994EJ6V0UD
40
(a) Interrupt enable flag (IE)
This flag controls interrupt request acknowledge operations of the CPU.
When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests are disabled.
When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with
an interrupt mask flag for various interrupt sources.
This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases.
(c) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all
other cases.
(d) Carry flag (CY)
This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It
stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit
operation instruction execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area (Other than the internal high-speed RAM area cannot be set as the stack
area).
Figure 3-9. Stack Pointer Configuration
0
15
SP14
SP15
SP
SP13 SP12 SP11 SP10
SP9
SP8
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The SP is decremented before writing (saving) to the stack memory and is incremented after reading
(restoring) from the stack memory.
Each stack operation saves/restores data as shown in Figures 3-10 and 3-11.
Cautions 1.
Since reset signal generation makes the SP contents undefined, be sure to initialize the
SP before using the stack memory.
2.
Stack pointers can be set only to the high-speed RAM area, and only the lower 10 bits
can be actually set.
Thus, if the stack pointer is specified to 0FF00H, it is converted to 0FB00H in the high-
speed RAM area, since 0FF00H is in the SFR area and not in the high-speed RAM area.
When the value is actually pushed onto the stack, 1 is subtracted from 0FB00H to
become 0FAFFH, but since that value is not in the high-speed RAM area, it is converted
to 0FEFFH, which is the same value as when 0FF00H is set to the stack pointer.
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