參數(shù)資料
型號: UPD78F9512GR-JJG-A
廠商: Renesas Electronics America
文件頁數(shù): 34/175頁
文件大?。?/td> 0K
描述: MCU 8BIT SGL CHIP 16PIN
標(biāo)準(zhǔn)包裝: 400
系列: 78K0S/Kx1+
核心處理器: 78K0S
芯體尺寸: 8-位
速度: 10MHz
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-SSOP(0.173",4.40mm 寬)
包裝: 托盤
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
User’s Manual U16994EJ6V0UD
127
Figure 6-39. Capture Register Data Retention Timing
Count clock
TM00 count value
Edge input
INTTM010
Capture read signal
CR010 capture value
N
N + 1
N + 2
M
M + 1
M + 2
X
N + 2
Capture, but
read value is
not guaranteed
Capture
M + 1
(15) Capture operation
<1>
If the valid edge of the TI000 pin is to be set as the count clock, do not set the clear/start mode and the
capture trigger at the valid edge of the TI000 pin.
<2>
When the CRC001 bit value is 1, capture is not performed in the CR000 register if both the rising and
falling edges have been selected as the valid edges of the TI000 pin.
<3>
When the CRC001 bit value is 1, the TM00 count value is not captured in the CR000 register when a
valid edge of the TI010 pin is detected, but the input from the TI010 pin can be used as an external
interrupt source because INTTM000 is generated at that timing.
<4>
To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two
cycles of the count clock selected by prescaler mode register 00 (PRM00).
<5>
The capture operation is performed at the fall of the count clock. An interrupt request input (INTTM0n0),
however, occurs at the rise of the next count clock.
<6>
To use two capture registers, set the TI000 and TI010 pins.
Remark
n = 0, 1
(16) Compare operation
The capture operation may not be performed for CR0n0 set in compare mode even if a capture trigger is input.
Remark
n = 0, 1
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