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參數(shù)資料
| 型號： | UPD98404 |
| 廠商： | NEC Corp. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 21/36頁 |
| 文件大小： | 201K |
| 代理商： | UPD98404 |
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Data Sheet S11822EJ4V0DS00
21
μ
PD98404
b) Internal register write
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Address setup time (to DS_B
↓
[WR_B
↓
])
t
SADDS
10
ns
CS_B setup time (to DS_B
↓
[WR_B
↓
])
t
SCSDS
5
9
×
t
CYTK
ns
R/W_B[RD_B] setup time
(to DS_B
↓
[WR_B
↓
])
t
SRWDS
5
ns
Data setup time (to DS_B
↑
[WR_B
↑
])
t
SDADS
15
ns
Address hold time (to DS_B
↑
[WR_B
↑
])
t
HADDS
4
ns
CS_B hold time (to DS_B
↑
[WR_B
↑
])
t
HCSDS
0
ns
R/W_B [WR_B] hold time
(to DS_B
↑
[WR_B
↑
])
t
HRWDS
4
ns
Data hold time (to DS_B
↑
[WR_B
↑
])
t
HDADS
4
ns
DS_B
↓
[WR_B
↓
]
→
ACK_B [RDY_B]
output delay time
t
VAKDS
Load capacity = 50 pF
15
ns
DS_B
↑
[WR_B
↑
]
→
ACK_B [RDY_B]
float delay time
t
IAKDSW
Load capacity = 50 pF
10
ns
DS_B [WR_B] pulse width
Note
t
WDS
50
ns
DS_B
↑
[WR_B
↑
]
→
DS_B
↓
[WR_B
↓
]
↓
recovery time
t
DSINT
4
×
t
CYTK
ns
Note
t
WDS
defines the time during which the
μ
PD98404 can recognize DS_B [WR_B] as a low level, and does not
define the pulse width of DS_B [WR_B] with which data can be accurately read.
The time required for the
μ
PD98404 to make ACK_B [RDY_B] low after DS_B [WR_B] has gone low differs
depending on the register to be accessed. Make DS_B [WR_B] high after confirming that ACK_B [RDY_B]
has gone low.
The time required for the
μ
PD98404 to make ACK_B [RDY_B] low after DS_B [WR_B] has gone low is “4 x
TCLK clock cycle (t
CYTK
)” at best. So that any register can be write without using ACK_B [RDY_B], widen
the pulse width of DS_B [WR_B] to at least to “4 x TCLK clock cycle”.
Remark
t
CYTK
is the cycle of the TCLK clock.
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