參數資料
型號： UPSD3254BV-40T1
廠商： 意法半導體
英文描述： POWERLINE: RP30-S_DE - 2:1 Wide Input Voltage Range- 30 Watts Output Power- 1.6kVDC Isolation- Fixed Operating Frequency- Six-Sided Continuous Shield- International Safety Standard Approvals- Ul 1950 Component Recognised- Standard 50.8 x40.6x10.2mm Package- Efficiency to 90%
中文描述： 閃存可編程系統(tǒng)設備與8032微控制器核心和256Kbit的SRAM
文件頁數： 122/176頁
文件大?。?/td> 1214K
代理商： UPSD3254BV-40T1
μPSD325X DEVICES
122/176
Decode PLD (DPLD)
The DPLD, shown in Figure 59, is used for decod-
ing the address for PSD MODULE and external
components. The DPLD can be used to generate
the following decode signals:
I
8 Sector Select (FS0-FS7) signals for the
primary Flash memory (three product terms
each)
I
4 Sector Select (CSBOOT0-CSBOOT3) signals
for the secondary Flash memory (three product
terms each)
I
1 internal SRAM Select (RS0) signal (two
product terms)
I
1 internal CSIOP Select signal (selects the PSD
MODULE registers)
I
2 internal Peripheral Select signals (Peripheral
I/O Mode).
Figure 59. DPLD Logic Array
Note: 1. Port A inputs are not available in the 52-pin package
2. Inputs from the MCU module
(INPUTS)
(24)
(8)
(16)
(1)
PDN (APD OUTPUT)
I/O PORTS (PORT A,B,C)1
(8)
PGR0 -PGR7
(8)
MCELLAB.FB [7:0] (FEEDBACKS)
MCELLBC.FB [7:0] (FEEDBACKS)
A[15:0]2
(2)
(4)
PD[2:1]
PSEN, RD, WR, ALE2
(1)
(1)
RESET 2
RD_BSY
RS0
CSIOP
PSEL0
PSEL1
8 PRIMARY FLASH
MEMORY SECTOR
SELECTS
SRAM SELECT
I/O DECODER
SELECT
PERIPHERAL I/O
MODE SELECT
CSBOOT 0
CSBOOT 1
CSBOOT 2
CSBOOT 3
FS0
FS7
3
3
3
3
3
3
3
3
3
3
3
3
2
AI06601
FS1
FS2
FS3
FS6
FS5
FS4
1
1
1
相關PDF資料
PDF描述
UPSD3253BV-40T1T Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM
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相關代理商/技術參數
參數描述
UPSD3254BV-40T1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
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UPSD3254BV-40T6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM
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